Datasheet

Phase Locked Loop Timing
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor 131
10.6 Phase Locked Loop Timing
Table 10-11 PLL Timing
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
f
osc
48—MHz
Internal reference relaxation oscillator frequency for the PLL
f
rosc
—8—MHz
PLL output frequency
2
(24 x reference frequency)
2. The core system clock will operate at 1/6 of the PLL output frequency.
f
op
96 192 — MHz
PLL lock time
3
3. This is the time required after the PLL is enabled to ensure reliable operation.
t
plls
—40100µs
Accumulated jitter using an 8MHz external crystal as the PLL source
4
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
J
A
— — 0.37 %
Cycle-to-cycle jitter
t
jitterpll
—350—ps