Datasheet

56F8035/56F8025 Data Sheet, Rev. 6
102 Freescale Semiconductor
• 0 = XTAL - External Crystal Oscillator Output (default)
• 1 = CLKIN - External Clock Input
6.3.20.3 Reserved—Bits 11–0
This bit field is reserved. Each bit must be set to 0.
6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width
Modulator (SIM_IPS0)
The internal integration of peripherals provides input signal source selection for peripherals where an input
signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral
type and provide a selection list for every peripheral input signal that has more than one alternative source
to indicate which source is selected.
If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the
settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select
an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral
input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control
of the I/O.
Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control
IPSn settings should not be altered while an affected peripheral is in an enabled (operational)
configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details.
GPIOA5_PEREN
Register
GPIOA5
GPIOA5 pin
SIM_IPS0
Register
PWM
FAULT2
Comparator A
Output (Internal)
0
1
0
1
01
00
10
PWM5
Timer A3
SIM_GPSA0
Register