56F8035/56F8025 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8025 Rev. 6 02/2010 freescale.
Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 5-3, changed the ITCN_BASE address from $00 F060 (incorrect value) to $00 F0E0 (the correct value). • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
Document Revision History Version History Rev.
56F8035/56F8025 General Description • Up to 32 MIPS at 32MHz core frequency • Two Analog Comparators • DSP and MCU functionality in a unified, C-efficient architecture • Three Programmable Interval Timers (PITs) • 56F8035 offers 64KB (32K x 16) Program Flash • One Queued Serial Communication Interface (QSCI) with LIN slave functionality • 56F8025 offers 32KB (16K x 16) Program Flash • One Queued Serial Peripheral Interfaces (QSPI) • 56F8035 offers 8KB (4K x 16) Unified Data/Program RAM • One 16-bit
6F8035/56F8025 Data Sheet Table of Contents Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 56F8035/56F8025 Features . . . . . . . . . . . 6 56F8035/56F8025 Description . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 9 Architecture Block Diagram . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . 17 Data Sheet Conventions . . . . . . . . . . . . . 17 7.3 Product Analysis. . . . . . . . . . . . .
Part 1 Overview 1.1 56F8035/56F8025 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8035/56F8025 Features 1.1.
— Full-duplex operation — Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions (2 to 16 bits) • One Inter-Integrated Circuit (I2C) port — Operates up to 400kbps — Supports both master and slave operation — Supports both 10-bit address mode and broadcasting mode • • Three 16-bit Programmable Interval Timers (PITs) Two analog Comparators (CMPs) — Selectable input source includes external pins, DACs — Programmable output polarity — Outp
Award-Winning Development Environment security systems, switched-mode power supply, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
additional information. The PWM_reload_sync output can be connected to the Timer’s Channel 3 input and the Timer’s Channels 2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0 and Timer Channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register; see Section 6.3.1.
Architecture Block Diagram To/From IPBus Bridge OCCS (ROSC / PLL / OSC) Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM GPIO D RESET (Muxed with GPIOA7) COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8035/56F8025 Data Sheet, Rev.
To/From IPBus Bridge IPBus INTC SYNC PIT0 MSTR_CNT_EN 3 MSTR_CNT_EN DAC SYNC on Figure 1-5 SYNC PIT1 MSTR_CNT_EN SYNC PIT2 2 3 Sync0, Sync1 Over/Under Limits SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on Figure 1-5 GPIOC2 ANA2 (VREFHA) GPIOC3 ANA3 (VREFLA) GPIOC1 ANA1 ADC ANB0 ANB0 on Figure 1-5 GPIOC6 ANB2 (VREFHB) GPIOC7 ANB3 (VREFLB) GPIOC5 ANB1 Figure 1-3 56F8035/56F8025 I/O Pin-Out Muxing (Part 1/5) 56F8035/56F8025 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge GPIOB6 - 7 QSCI0 RXD0, TXD0 2 TA2, TA3 on Figure 1-7 GPIOB2 - 3 MISO0, MOSI0 QSPI0 SCLK0, SS0 2 2 2 I2C SCL, SDA 2 GPIOB0 - 1 2 IPBus Figure 1-4 56F8035/56F8025 I/O Pin-Out Muxing (Part 2/5) 56F8035/56F8025 Data Sheet, Rev.
To/From IPBus Bridge FAULT1 on Figure 1-6 GPIOA8 TA2 on Figure 1-7 CMP_IN1 CMP_IN3 CMPAI1 CMPAI3 GPIOC0 CMPA CMP_OUT CMP_IN2 CMPAO on Figure 1-6, Figure 1-7 CMPAI2 GPIOA10 ANA0 on Figure 1-3 Export Import TB2 on Figure 1-4 GPIOB10 DAC0 2 3 TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 DAC1 GPIOB11 Import Export CMP_IN2 CMP_OUT ANB0 on Figure 1-3 GPIOA11 CMPBI2 CMPBO on Figure 1-6, Figure 1-7 CMPB GPIOC4 CMP_IN3 CMP_IN1 CMPBI3 CMPBI1 GPIOA9 TA3 on Figure 1-7 FAULT2 on
Architecture Block Diagram To/From IPBus Bridge TA0 on Figure 1-7 GPIOA6 2 TA2 - 3 on Figure 1-7 GPIOA0 - 3 4 PWM0 - 3 FAULT0 2 PWMA4 - 5 1 GPIOA4 - 5 2 PWM FAULT1 FAULT1 on Figure 1-5 FAULT2 RELOAD PSRC0 - 1 1 FAULT3 FAULT2 on Figure 1-5 TA1 on Figure 1-7 GPIOB5 RELOAD on Figure 1-7, Figure 1-5 IPBus CMPAO on Figure 1-5 CMPBO on Figure 1-5 3 3 3 3 GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3 Figure 1-6 56F8035/56F8025 I/O Pin-Out Muxing (Part 4/5) 5
To/From IPBus Bridge TA0o on Figure 1-6 (PWM) T0o T0i TA0 on Figure 1-6 (GPIOA6) T1o T1i TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TMRA TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o TA2 on Figure 1-5 (GPIOA8) T2i TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) T3o TA3 on Figure 1-5 (GPIOA9) T3i TA3 on Figure 1-4 (GPIOB3) RELOAD on Figure 1-6 (PWM) IPBus Figure 1-7
Product Documentation 1.5 Product Documentation The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8035/56F8025. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8035/56F8025 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number.
Introduction In Table 2-2, peripheral pins in bold identify reset state.
Table 2-2 56F8035/56F8025 Pins (Continued) Peripherals: Pin # Pin Name 28 VSS_IO VSS VSS 29 VDD_IO VDD VDD 30 GPIOB0 GPIOB0, SCLK0, SCL B0 31 GPIOA4 GPIOA4, PWM4, TA2, FAULT1 A4 PWM4 FAULT1 32 GPIOA2 GPIOA2, PWM2 A2 PWM2 33 GPIOA3 GPIOA3, PWM3 A3 PWM3 34 VCAP VCAP VCAP 35 VDD_IO VDD VDD 36 VSS_IO VSS VSS 37 GPIOD5 GPIOD5, XTAL, CLKIN D5 XTAL CLKIN 38 GPIOD4 GPIOD4, EXTAL D4 EXTAL 39 GPIOA1 GPIOA1, PWM1 A1 PWM1 40 GPIOA0 GPIOA0, PWM0 A0 PWM0 41 TD
Introduction VDD Power VSS Ground VDDA Power VSSA Ground Other Supply Ports VCAP 2 3 1 1 4 GPIOA0-3 (PWM0-3) GPIOA4 (PWM4, TA2, FAULT1) 1 GPIOA5 (PWM5, TA3, FAULT2) 1 GPIOA6 (FAULT0, TA0) 1 56F8035/56F802 1 2 GPIOA8 (FAULT1, TA2, CMPAI1) PWM or TMRA or CMP or GPIOA GPIOA9 (FAULT2, TA3, CMPBI1) 1 GPIOD4 (EXTAL) OSC Port or GPIO GPIOA10 (CMPAI2) 1 1 1 1 GPIOA11 (CMPBI2) GPIOD5 (XTAL, CLKIN) RESET or GPIOA RESET (GPIOA7) 1 GPIOB0 (SCLK0, SCL) QSPI or I2C or PWM or TMRA or GPIOB 1 G
2.2 56F8035/56F8025 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 29 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 35 VSS 17 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.
56F8035/56F8025 Signal Pins Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOA0 40 (PWM0) Type Input/ Output State During Reset Input, internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOA4 31 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM4) Output PWM4 — This is one of the six PWM output pins.
56F8035/56F8025 Signal Pins Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOA6 24 (FAULT0) Type Input/ Output State During Reset Input, internal pull-up enabled Input Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (TA0) TA0 — Timer A, Channel 0.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOA10 25 (CMPAI2) Type Input/ Output Input State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Comparator A, Input 2 — This is an analog input to Comparator A. After reset, the default state is GPIOA10. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
56F8035/56F8025 Signal Pins Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOB2 23 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO0) Input/ Output QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOB5 4 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (TA1) Input/ Output (FAULT3) Input FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip.
56F8035/56F8025 Signal Pins Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOB10 20 (CMPAO) Type Input/ Output Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Comparator A Output— This is the output of comparator A. After reset, the default state is GPIOB10. The peripheral functionality is controlled via the SIM. See Section 6.3.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOC3 13 Type Input/ Output State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANA3) Analog Input ANA3 — Analog input to ADC A, Channel 3. (VREFLA) Analog Input VREFLA — Analog reference voltage low (ADC A). After reset, the default state is GPIOC3.
56F8035/56F8025 Signal Pins Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. GPIOC7 10 Type Input/ Output (ANB3) Analog Input (VREFLB) Input State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. VREFLB — Analog reference voltage low (ADC B). After reset, the default state is GPIOC7.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal Name LQFP Pin No. Type TDO 44 Output (GPIOD1) State During Reset Output tri-stated, internal pull-up enabled Input/ Output Signal Description Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK.
Overview Part 3 OCCS 3.1 Overview The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual. 3.
The 56F8000 family devices’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CTRL) Divide-by Register (OCCS_DIVBY) Status Register (OCCS_STAT) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference Manual. 3.
Ceramic Resonator Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 KΩ Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg Ω CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz.
56F8035/56F8025 CLKMODE = 1 XTAL EXTAL External Clock GND or GPIO Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input.
Interrupt Vector Table Table 4-1 Chip Memory Configurations On-Chip Memory 56F8035 56F8025 Use Restrictions Program Flash (PFLASH) 32K x 16 16K x 16 or 64KB or 32KB Erase/Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4K x 16 or 8KB 2K x 16 or 4KB Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8035/56F8025’s reset and interrupt priority structure, including on-chip peripherals.
Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data, and Address Buffers Empty 20-23 Reserved GPIOD 24 0-2 P:$30 GPIOD GPIOC 25 0-2 P:$32 GPIOC GPIOB 26 0-2 P:$34 GPIOB GPIOA 27 0-2 P:$36 GPIOA QSPI0 28 0-2 P:$38 QSPI0 Receiver Full 29 0-2 P:$3A QSPI0 30-31 QSPI0 T
Program Map 4.3 Program Map The Program Memory map is shown in Table 4-3 and Table 4-4. Table 4-3 Program Memory Map1 at Reset for 56F8035 Begin/End Address Memory Allocation P: $1F FFFF P: $00 9000 RESERVED P: $00 8FFF P: $00 8000 On-Chip RAM2 8KB P: $00 7FFF P: $00 0000 Internal Program Flash 64KB Cop Reset Address = $00 0002 Boot Location = $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.
Table 4-5 Data Memory Map1 for 56F8035 (Continued) Begin/End Address Memory Allocation X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 8800 RESERVED X:$00 87FF X:$00 8000 RESERVED X:$00 7FFF X:$00 1000 RESERVED X:$00 0FFF X:$00 0000 On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1.
EOnCE Memory Map Program Data EOnCE Reserved Reserved RAM Peripherals Dual Port RAM Reserved Flash RAM Figure 4-1 Dual Port RAM for 56F8035 Program Data EOnCE Reserved Reserved RAM Peripherals Flash Dual Port RAM Reserved Reserved RAM Figure 4-2 Dual Port RAM for 56F8025 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-7 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 Register Name Reserved OCR Control Register X:$FF FF9F Instruction Step Counter X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9D OSR Status Register X:$FF FF9C OBASE Peripheral Base Address Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9A OTBPR Trace Buffer Pointer Register X:$FF FF99 Trace Buffer Register Stages X:$FF FF98 OTB (21 - 24 bits/stage) Tra
Peripheral Memory-Mapped Registers Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number ADC ADC X:$00 F080 4-10 PWM PWM X:$00 F0C0 4-11 ITCN ITCN X:$00 F0E0 4-12 SIM SIM X:$00 F100 4-13 COP COP X:$00 F120 4-14 CLK, PLL, OSC OCCS X:$00 F130 4-15 Power Supervisor PS X:$00 F140 4-16 GPIO Port A GPIOA X:$00 F150 4-17 GPIO Port B GPIOB X:$00 F160 4-18 GPIO Port C GPIOC X:$00 F170 4-19 GPIO Port D GPIOD X:$
Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA0_ENBL $F Timer Channel Enable Register TMRA1_COMP1 $10 Compare Register 1 TMRA1_COMP2 $11 Compare Register 2 TMRA1_CAPT $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCTRL $17 Status and Control Register TMRA1_CMPLD1 $18 Comparator Load Re
Peripheral Memory-Mapped Registers Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA3_CSCTRL $3A Comparator Status and Control Register TMRA3_FILT $3B Input Filter Register Reserved Table 4-10 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_CTRL1 $0 Control Register 1 ADC_CTRL2 $1 Control Register 2 ADC_ZXCTRL $2 Zero Cr
Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_LOLIM1 $1D Low Limit Register 1 ADC_LOLIM2 $1E Low Limit Register 2 ADC_LOLIM3 $1F Low Limit Register 3 ADC_LOLIM4 $20 Low Limit Register 4 ADC_LOLIM5 $21 Low Limit Register 5 ADC_LOLIM6 $22 Low Limit Register 6 ADC_LOLIM7 $23 Low Limit Register 7 ADC_HILIM0 $24 High Limit Register 0 ADC_HILIM1 $25 High Limit Register 1 ADC_HILI
Peripheral Memory-Mapped Registers Table 4-11 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_VAL1 $7 Value Register 1 PWM_VAL2 $8 Value Register 2 PWM_VAL3 $9 Value Register 3 PWM_VAL4 $A Value Register 4 PWM_VAL5 $B Value Register 5 PWM_DTIM0 $C Dead Time Register 0 PWM_DTIM1 $D Dead Time Register 1 PWM_DMAP1 $E Disable Mapping Register 1 PWM_DMAP2 $F Disable Mapping Register 2 PWM_CNFG $
Table 4-12 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F0E0) Register Acronym Address Offset Register Description ITCN_IRQP0 $E IRQ Pending Register 0 ITCN_IRQP1 $F IRQ Pending Register 1 ITCN_IRQP2 $10 IRQ Pending Register 2 ITCN_IRQP3 $11 IRQ Pending Register 3 Reserved ITCN_ICTRL $16 Interrupt Control Register Reserved Table 4-13 SIM Registers Address Map (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register
Peripheral Memory-Mapped Registers Table 4-13 SIM Registers Address Map (Continued) (SIM_BASE = $00 F100) Register Acronym SIM_IPS2 Address Offset $1A Register Description Internal Peripheral Source Select Register 2 for TMRA Reserved Table 4-14 Computer Operating Properly Registers Address Map (COP_BASE = $00 F120) Register Acronym COP_CTRL Address Offset $0 Register Description Control Register COP_TOUT $1 Time-Out Register COP_CNTR $2 Counter Register Table 4-15 Clock Generation Module Regis
Table 4-17 GPIOA Registers Address Map (GPIOA_BASE = $00 F150) Register Acronym GPIOA_PUPEN Address Offset $0 Register Description Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register GPIOA_IASSRT $4 Interrupt Assert Register GPIOA_IEN $5 Interrupt Enable Register GPIOA_IEPOL $6 Interrupt Edge Polarity Register GPIOA_IPEND $7 Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register GP
Peripheral Memory-Mapped Registers Table 4-19 GPIOC Registers Address Map (GPIOC_BASE = $00 F170) Register Acronym Address Offset Register Description GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IEPOL $6 Interrupt Edge Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register GPIOC
Table 4-20 GPIOD Registers Address Map (GPIOD_BASE = $00 F180) Register Acronym Address Offset Register Description GPIOD_PUPEN $0 Pull-up Enable Register GPIOD_DATA $1 Data Register GPIOD_DDIR $2 Data Direction Register GPIOD_PEREN $3 Peripheral Enable Register GPIOD_IASSRT $4 Interrupt Assert Register GPIOD_IEN $5 Interrupt Enable Register GPIOD_IEPOL $6 Interrupt Edge Polarity Register GPIOD_IPEND $7 Interrupt Pending Register GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register
Peripheral Memory-Mapped Registers Table 4-23 Programmable Interval Timer 2 Registers Address Map (Continued) (PIT2_BASE = $00 F1B0) Register Acronym Address Offset Register Description PIT2_MOD $1 Modulo Register PIT2_CNTR $2 Counter Register Table 4-24 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0) Register Acronym DAC0_CTRL Address Offset $0 Register Description Control Register DAC0_DATA $1 Data Register DAC0_STEP $2 Step Register DAC0_MINVAL $3 Minimum V
Table 4-27 Comparator B Registers Address Map (Continued) (CMPB_BASE = $00 F1F0) Register Acronym CMPB_FILT Address Offset Register Description $2 Filter Register Table 4-28 Queued Serial Communication Interface 0 Registers Address Map (QSCI0_BASE = $00 F200) Register Acronym Address Offset Register Description QSCI0_RATE $0 Baud Rate Register QSCI0_CTRL1 $1 Control Register 1 QSCI0_CTRL2 $2 Control Register 2 QSCI0_STAT $3 Status Register QSCI0_DATA $4 Data Register Table 4-29 Queued
Peripheral Memory-Mapped Registers Table 4-30 I2C Registers Address Map (Continued) (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_RISTAT $1A Raw Interrupt Status Register I2C_RXFT $1C Receive FIFO Threshold Register I2C_TXFT $1E Transmit FIFO Threshold Register I2C_CLRINT $20 Clear Combined and Individual Interrupts Register I2C_CLRRXUND $22 Clear RX_UNDER Interrupt Register I2C_CLRRXOVR $24 Clear RX_OVER Interrupt Register I2C_CLRTXOVR $26 Clear TX_O
Table 4-31 Flash Module Registers Address Map (FM_BASE = $00 F400) (Continued) Register Acronym Address Offset FM_IFROPT_1 FM_TSTSIG Register Description $1B Information Option Register 1 $1C Reserved $1D Test Array Signature Register Part 5 Interrupt Controller (ITCN) 5.
Functional Description and I1 bits in its status register. 56F8035/56F8025 Data Sheet, Rev.
Table 5-1 Interrupt Mask Bit Definition SR[9] (I1) SR[8] (I0) Exceptions Permitted Exceptions Masked 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E core. Table 5-2 Interrupt Priority Encoding 5.3.
Block Diagram 5.4 Block Diagram any0 Priority Level INT1 Level 0 64 -> 6 Priority Encoder 2 -> 4 Decode 6 INT VAB CONTROL any3 Level 3 IACK SR[9:8] Priority Level INT64 IPIC 64 -> 6 Priority Encoder 6 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default.
Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F0E0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.5 IPR5 $5 Interrupt Priority Register 5 5.6.6 IPR6 $6 Interrupt Priority Register 6 5.6.7 VBA $7 Vector Base Address Register 5.6.
Register Descriptions Add.
5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 Read 15 14 13 PLL IPL Write RESET 0 0 12 11 10 0 0 0 0 LVI IPL 0 0 9 8 RX_REG IPL 0 0 7 6 TX_REG IPL 0 0 5 4 TRBUF IPL 0 0 3 2 BKPT_U IPL 0 0 1 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.
Register Descriptions 5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.
5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read 15 14 GPIOD IPL Write RESET 0 0 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 FM_CBE IPL 0 0 3 2 FM_CC IPL 0 0 1 0 FM_ERR IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
Register Descriptions 5.6.2.5 FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0 This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
5.6.3.4 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6 This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for the GPIOA IRQ.
Register Descriptions 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14 This field is used to set the interrupt priority level for the I2C Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 Reserved—Bits 13–6 This bit field is reserved. Each bit must be set to 0. 5.6.4.
5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 TMRA_3 IPL Write RESET 0 0 13 12 TMRA_2 IPL 0 0 11 10 TMRA_1 IPL 0 0 9 8 TMRA_0 IPL 0 0 7 6 I2C_STAT IPL 0 0 5 4 I2C_TX IPL 0 0 3 2 I2C_RX IPL 0 0 1 0 I2C_GEN IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ.
Register Descriptions 5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
• • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 Read Write RESET 15 14 13 12 PIT1 IPL PIT0 IPL 0 0 0 0 11 10 COMPB IPL 0 0 9 8 COMPA IPL 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR6) 5.6.6.
Register Descriptions 5.6.6.4 Comparator A Interrupt Priority Level (COMPA IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 5.6.
5.6.7.4 ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
Register Descriptions 5.6.8 Vector Base Address Register (VBA) Base + $7 15 14 Read 0 0 0 0 13 12 11 10 9 7 6 5 4 3 2 1 0 0 0 0 0 0 VECTOR_BASE_ADDRESS Write RESET1 8 0 0 0 0 0 0 1 0 0 1. The 56F8035 resets to a value of 0 x 0000. This corresponds to reset addresses of 0 x 000000. The 56F8025 resets to a value of 0 x 0080. This corresponds to reset addresses of 0 x 004000. Figure 5-10 Vector Base Address Register (VBA) 5.6.8.
5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $9 15 14 13 12 11 Read 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0.
Register Descriptions Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 5.6.
5.6.15.1 IRQ Pending (PENDING)—Bits 16–2 These register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.15.2 Reserved—Bit 0 This bit field is reserved. It must be set to 1. 5.6.
Register Descriptions 5.6.18 IRQ Pending Register 3 (IRQP3) Base + $11 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[63:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-20 IRQ Pending Register 3 (IRQP3) 5.6.18.1 IRQ Pending (PENDING)—Bits 63–49 These register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending IRQ numbers correspond to ascending bit locations.
Table 5-4 Interrupt Priority Encoding 5.6.19.3 IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority 00 No interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priority 2 or 3 Priority 3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.
Introduction 5.7.2 Description of Reset Operation 5.7.2.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-22. RES CLK VAB RESET_VECTOR_ADR PAB READ_ADR Figure 5-22 Reset Interface 5.7.3 ITCN After Reset After reset, all of the ITCN registers are in their default states.
6.
Register Descriptions 6.3 Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.
Add.
Register Descriptions Reserved 0 = Read as 0 = Read as 1 1 = Reserved Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 6.3.1.
6.3.2 SIM Reset Status Register (SIM_RSTAT) This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs.
Register Descriptions 6.3.2.7 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow.
6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption.
Register Descriptions 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.2 • • PWM3—Bit 9 0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock 6.3.7.3 • • PWM2—Bit 8 0 = Peripheral output function of GPIOA[2] is defined to be PWM2 1 = Peripheral output function of GPIOA[2] is defined to be the system clock 6.3.7.
6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14 This bit selects the clock speed for the Quad Timer A module. • • 0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13 This bit selects the clock speed for the PWM module.
Register Descriptions 6.3.9.3 • • 0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled) 1 = The clock is enabled to the DAC1 module 6.3.9.4 • • Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13 Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12 0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled) 1 = The clock is enabled to the DAC0 module 6.3.9.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.9.
• 1 = The clock is enabled to the PWM module 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1) See Section 6.3.9 for general information about Peripheral Clock Enable registers. Base + $D 15 Read 0 14 13 12 PIT2 PIT1 PIT0 0 0 0 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 3 2 1 0 TA3 TA2 TA1 TA0 0 0 0 0 Write RESET 0 0 0 0 0 0 0 0 0 Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1) 6.3.10.1 Reserved—Bit 15 This bit field is reserved.
Register Descriptions 6.3.10.9 • • Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) 1 = The clock is enabled to the Timer A0 module 6.3.11 Stop Disable Register 0 (SD0) By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This register will allow an individual peripheral to operate in Stop mode.
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.11.6 • • Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.7 Reserved—Bits 9–7 This bit field is reserved. Each bit must be set to 0. 6.3.
Register Descriptions 6.3.12 Stop Disable Register 1 (SD1) See Section 6.3.11 for general information about Stop Disable Registers. Base + $F 15 Read 0 PIT2_ SD 0 0 Write RESET 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIT1_ SD PIT0_ SD 0 0 0 0 0 0 0 0 TA3_ SD TA2_ SD TA1_ SD TA0_ SD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-13 Stop Disable Register 1 (SD1) 6.3.12.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.12.
6.3.12.8 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.9 • • Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.
Register Descriptions Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ISAL[23:22] Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.13.1 Reserved—Bits 15—2 This bit field is reserved. Each bit must be set to 0. 6.3.13.
Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 PCEP Write RESET 2 0 0 GIPSP 0 0 0 Figure 6-17 Protection Register (SIM_PROT) 6.3.15.1 Reserved—Bits 15–4 This bit field is reserved. Each bit must be set to 0. 6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2 These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
Register Descriptions GPIOA6_PEREN Register SIM_GPSA0 Register PWM FAULT0 GPIOA6 0 GPIOA6 pin 0 1 1 Timer A0 Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one of these I/O must be configured to control that peripheral function.
• • • 01 = FAULT2 - PWM FAULT2 Input 10 = TA3 - Timer A3 11 = Reserved 6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8 This field selects the alternate function for GPIOA4. • • • • 00 = PWM4 - PWM4 (default) 01 = FAULT1 - PWM FAULT1 Input 10 = TA2 - Timer A2 11 = Reserved 6.3.16.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Register Descriptions • • • • 00 = FAULT2 - PWM FAULT2 Input (default) 01 = TA3 - Timer A3 10 = CMPBI1 - Comparator B Input 1 11 = Reserved 6.3.17.6 Configure GPIOA8 (GPS_A8)—Bits 1–0 This field selects the alternate function for GPIOA8. • • • • 00 = FAULT1 - PWM FAULT1 Input (default) 01 = TA2 - Timer A2 10 = CMPAI1 - Comparator A Input 1 11 = Reserved 6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0) See Section 6.3.
6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6 This field selects the alternate function for GPIOB3. • • • • 00 = MOSI0 - QSPI0 Master Out/Slave In (default) 01 = TA3 - Timer A3 10 = PSRC1 - PWM2/PWM3 Pair External Source 11 = Reserved 6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4 This field selects the alternate function for GPIOB2. • • • • 00 = MISO0 QSPI0 Master In/Slave Out (default) 01 = TA2 - Timer A2 10 = PSRC0 - PWM0/PWM1 Pair External Source 11 = Reserved 6.3.18.
Register Descriptions 6.3.19.1 Reserved—Bits 15–9 This bit field is reserved. Each bit must be set to 0. 6.3.19.2 Configure GPIOB11 (GPS_B11)—Bit 8 This field selects the alternate function for GPIOB11. • • 0 = CMPBO - Comparator B Output (default) 1 = Reserved 6.3.19.3 Reserved—Bit 7 This bit field is reserved. It must be set to 0. 6.3.19.4 Configure GPIOB10 (GPS_B10)—Bit 6 This field selects the alternate function for GPIOB10. • • 0 = CMPAO - Comparator A Output (default) 1 = Reserved 6.3.
• • 0 = XTAL - External Crystal Oscillator Output (default) 1 = CLKIN - External Clock Input 6.3.20.3 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. 6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width Modulator (SIM_IPS0) The internal integration of peripherals provides input signal source selection for peripherals where an input signal to a peripheral can be fed from one of several sources.
Register Descriptions Base + $18 15 14 13 12 11 10 9 Read 0 0 IPS0_ FAULT2 0 IPS0_ FAULT1 0 0 0 0 0 0 0 0 0 Write RESET 8 7 6 5 IPS0_PSRC2 0 0 4 3 2 IPS0_PSRC1 0 0 0 1 0 IPS0_PSRC0 0 0 0 0 Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0) 6.3.21.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 6.3.21.
• • 11x = Reserved 1x1 = Reserved 6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)—Bits 5–3 This field selects the alternate input source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair source.
Register Descriptions Base + $19 15 14 13 12 11 10 9 8 7 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 4 0 0 3 0 IPS1_DSYNC1 Write RESET 5 0 0 2 1 0 IPS1_DSYNC0 0 0 0 Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1) 6.3.22.1 Reserved—Bits 15–7 This bit field is reserved. Each bit must be set to 0. 6.3.22.
Base + $1A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 IPS2_ TA3 0 0 0 IPS2_ TA2 0 0 0 IPS2_ TA1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2) 6.3.23.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.23.2 Select Input Source for TA3 (IPS2_TA3)—Bit 12 This field selects the alternate input source signal to feed Quad Timer A, input 3.
Clock Generation Overview master clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and can be an optional clock for PWM, Timer A, Timer B, and I2C modules. These clocks are generated by gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls.
6.5 Power-Saving Modes The 56F8035/56F8025 operates in one of five Power-Saving modes, as shown in Table 6-2. Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications.
Resets default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
EXTENDED_POR JTAG POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock Memory Subsystem CLKGEN_RST OCCS COMBINED_RST External RESET IN (active low) PERIP_RST Delay 32 OSC_CLK Clock RESET Peripherals pulse shaper Delay 32 sys clocks COP_TOR (active low) SW Reset pulse shaper COP_LOR (active low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles.
Clocks The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset.
Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-29 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts.
Flash Access Lock and Unlock Mechanisms security mode is enabled, the 56F8025 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU.
in order to return to normal unsecured operation. Power-on reset will also reset both. The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.
Configuration Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 40 Defaults to A0 GPIOA1 PWM1 39 Defaults to A1 GPIOA2 PWM2 32 Defaults to A2 GPIOA3 PWM3 33 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 31 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 27 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2.
Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB3 MOSI0 / TA3 / PSRC1 22 SIM register SIM_GPS is used to select between MOSI0, TA3 and PSRC1. Defaults to B3 GPIOB5 TA1 / FAULT3 / CLKIN 4 SIM register SIM_GPS is used to select between TA1, FAULT3, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block.
Reset Values Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOD0 TDI 41 Defaults to TDI GPIOD1 TDO 44 Defaults to TDO GPIOD2 TCK 19 Defaults to TCK GPIOD3 TMS 43 Defaults to TMS GPIOD4 EXTAL 38 Defaults to D4 GPIOD5 XTAL / CLKIN 37 SIM register SIM_GPSCD is used to select between XTAL and CLKIN. Defaults to D5 8.
Add. Offset Register Acronym $0 GPIOA_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE 15 14 13 12 R W RS 0 0 0 0 0 1 1 1 R W RS .0 .0 .0 .0 0 0 0 0 . 0. .0. . 0. 0 0 0 R . 0.
Reset Values Add.
Add.
Reset Values Add.
Part 9 Joint Test Action Group (JTAG) 9.1 56F8035/56F8025 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual. Part 10 Specifications 10.
General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.
Table 10-2 56F8035/56F8025 ESD Protection Characteristic Min Typ Max Unit ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 750 — — V Table 10-3 LQFP Package Thermal Characteristics6 Characteristic Comments Symbol Value (LQFP) Unit Notes RθJA 41 °C/W 2 Junction to ambient Natural convection Single layer board (1s) Junction to ambient Natural convection Four layer board (2s2p) RθJMA 34 °C/W 1, 2 Junction to ambient (@200 ft/min) Single layer board (1s)
General Characteristics Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Symbol Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V VREFHx 3.0 VDDA V Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 0 0.
10.2 DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4V to 5.
DC Electrical Characteristics 2.0 0.0 µA - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Volt Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled) Table 10-6 Current Consumption per Power Supply Pin Typical @ 3.3V, 25°C Mode Maximum@ 3.6V, 25°C Conditions IDD1 IDDA IDD1 IDDA RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled.
Table 10-6 Current Consumption per Power Supply Pin (Continued) Typical @ 3.3V, 25°C Mode Maximum@ 3.
AC Electrical Characteristics and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8. Table 10-8. Regulator Parameters Characteristic Short Circuit Current Short Circuit Tolerance (VCAP shorted to ground) Symbol Min Typical Max Unit ISS — 450 650 mA TRSC — — 30 minutes 10.
10.4 Flash Memory Characteristics Table 10-9 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — 40 μs Erase time 2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory. 10.
Phase Locked Loop Timing 10.6 Phase Locked Loop Timing Table 10-11 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 — MHz Internal reference relaxation oscillator frequency for the PLL frosc — 8 — MHz PLL output frequency2 (24 x reference frequency) fop 96 192 — MHz PLL lock time3 tplls — 40 100 µs Accumulated jitter using an 8MHz external crystal as the PLL source4 JA — — 0.
10.7 Relaxation Oscillator Timing Table 10-12 Relaxation Oscillator Timing Characteristic Symbol Minimum Typical Maximum Relaxation Oscillator output frequency1 Normal Mode Standby Mode fop — Relaxation Oscillator stabilization time2 troscs — 1 3 ms tjitterrosc — 400 — ps Minimum tuning step size — .08 — % Maximum tuning step size — 40 — % Variation over temperature -40°C to 150ºC4 — Variation over temperature 0°C to 105ºC4 — — 8.05 200 Cycle-to-cycle jitter.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing .
10.9 Serial Peripheral Interface (SPI) Timing Table 10-14 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 125 62.5 — — ns ns — 31 — — ns ns — 125 — — ns ns 50 31 — — ns ns 50 31 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing 1. Parameters listed are guaranteed by design. SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in tDI MOSI (Output) Master MSB out Bits 14–1 tDV Bits 14–1 tF LSB in tDI(ref) Master LSB out tR Figure 10-7 SPI Master Timing (CPHA = 0) 56F8035/56F8025 Data Sheet, Rev.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Master MSB out tDH Bits 14–1 tDV Bits 14– 1 tF LSB in tDI(ref) Master LSB out tR Figure 10-8 SPI Master Timing (CPHA = 1) 56F8035/56F8025 Data Sheet, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDV tDH MSB in tF tR Bits 14–1 tDS MOSI (Input) tELG tR Bits 14–1 tD Slave LSB out tDI tDI LSB in Figure 10-9 SPI Slave Timing (CPHA = 0) 56F8035/56F8025 Data Sheet, Rev.
SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV tDI tDH MOSI (Input) MSB in Slave LSB out Bits 14–1 LSB in Figure 10-10 SPI Slave Timing (CPHA = 1) 10.
Quad Timer Timing Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 10-11 Timer Timing 56F8035/56F8025 Data Sheet, Rev.
10.11 Serial Communication Interface (SCI) Timing Table 10-16 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width TXDPW 0.965/BR 1.
Inter-Integrated Circuit Interface (I2C) Timing 10.12 Inter-Integrated Circuit Interface (I2C) Timing Table 10-17 I2C Timing Standard Mode Characteristic Fast Mode Symbol Unit Minimum Maximum Minimum Maximum fSCL 0 100 0 400 kHz tHD; STA 4.0 — 0.6 — μs LOW period of the SCL clock tLOW 4.7 — 1.23 — μs HIGH period of the SCL clock tHIGH 4.0 — 0.6 — μs Set-up time for a repeated START condition tSU; STA 4.7 — 0.6 — μs Data hold time for I2C bus devices tHD; DAT 01 3.
SDA tf tLOW tSU; DAT tr tf tHD; STA tSP tr tBUF SCL S tHD; STA tSU; STA tHD; DAT tHIGH SR tSU; STO P S Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus 56F8035/56F8025 Data Sheet, Rev.
JTAG Timing 10.13 JTAG Timing Table 10-18 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 fOP DC SYS_CLK/8 MHz 10-15 TCK clock pulse width tPW 50 — ns 10-15 TMS, TDI data set-up time tDS 5 — ns 10-16 TMS, TDI data hold time tDH 5 — ns 10-16 TCK low to TDO data valid tDV — 30 ns 10-16 TCK low to TDO tri-state tTS — 30 ns 10-16 1. TCK frequency of operation must be less than 1/8 the processor rate.
10.14 Analog-to-Digital Converter (ADC) Parameters Table 10-19 ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.
Equivalent Circuit for ADC Inputs 5. LSB = Least Significant Bit = 0.806mV 6. Pin groups are detailed following Table 10-1. 7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC. 10.15 Equivalent Circuit for ADC Inputs Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open.
10.16 Comparator (CMP) Parameters Table 10-20 CMP Parameters Characteristic Conditions/Comments Symbol Min Typ Max Unit Within range of VDDA - .1V to VSSA + .1V VOFFSET — ±10 ±35 mV Input Propagation Delay tPD — 35 45 ns Power-up time tCPU — TBD TBD Input Offset Voltage1 1. No guaranteed specification within 0.1V of VDDA or VSSA 10.
Digital-to-Analog Converter (DAC) Parameters Table 10-21 DAC Parameters (Continued) Parameter Conditions/Comments Symbol Min Typ Max Unit AC Specifications Signal-to-noise ratio SNR — TBD — dB Spurious free dynamic range SFDR — TBD — dB Effective number of bits ENOB 9 — — bits 1. No guaranteed specification within 5% of VDDA or VSSA 2. LSB = 0.806mV 56F8035/56F8025 Data Sheet, Rev.
10.18 Power Consumption See Section 10.1 for a list of IDD requirements for the 56F8035/56F8025. This section provides additional detail which can be used to optimize power consumption for a given application.
56F8035/56F8025 Package and Pin-Out Information • Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations.
GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL VCAP VDD VSS GPIOD5 / XTAL / CLKIN GPIOD4 / EXTAL GPIOA1 / PWM1 GPIOA0 / PWM0 TDI / GPIOD0 GPIOB11 / CMPBO TMS / GPIOD3 TDO / GPIOD1 ORIENTATION MARK GPIOB6 / RXD0 / SDA / CLKIN GPIOA3 / PWM3 GPIOA2 / PWM2 PIN 34 GPIOA4 / PWM4 / TA2 / FAULT1 PIN 1 GPIOB5 / TA1 / FAULT3 / CLKIN GPIOB0 / SCLK0 / SCL GPIOA9 / FAULT2 / TA3 / CMPBI1 VDD GPIOA11 / CMPBI2 VSS GPIOC4 / ANB0 & CMPBI3 GPIOA5 / PWM5 / TA3 / FAULTA2 GPIOC5 / ANB1 GPIOA8 / FAULTA1 / TA2 /
56F8035/56F8025 Package and Pin-Out Information Table 11-1 56F8035/56F8025 44-Pin LQFP Package Identification by Pin Number1 Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 GPIOB6 RXD0 / SDA / CLKIN 12 VSSA 23 GPIOB2 MISO0 / TA2 / PSRC0 34 VCAP 2 GPIOB1 SS0 / SDA 13 GPIOC3 ANA3 / VREFLA 24 GPIOA6 FAULT0 / TA0 35 VDD 3 GPIOB7 TXD0 / SCL 14 GPIOC2 ANA2 / VREFHA 25 GPIOA10 CMPAI2 36 VSS 4 GPIOB5 TA1 / FAULT3 / CLKIN 15 GPIOC1 ANA1 26 GPIOA8 FAULT1
Figure 11-2 56F8035/56F8025 44-Pin LQFP Mechanical Information (1 of 3) Please see www.freescale.com for the most current case outline. 56F8035/56F8025 Data Sheet, Rev.
56F8035/56F8025 Package and Pin-Out Information Figure 11-3 56F8035/56F8025 44-Pin LQFP Mechanical Information (2 of 3) Please see www.freescale.com for the most current case outline. 56F8035/56F8025 Data Sheet, Rev.
Figure 11-4 56F8035/56F8025 44-Pin LQFP Mechanical Information (3 of 3) Please see www.freescale.com for the most current case outline. 56F8035/56F8025 Data Sheet, Rev.
Thermal Design Considerations Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Electrical Design Considerations • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended.
Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table.
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Inter-Integrated Circuit Interface (I2C) Module Control Register CTRL I2C_CTRL I2C_IBCR I2C_IBCR 0xF280 Target Address Register TAR IBCR I2C_TAR I2CTAR I2C_TAR 0xF282 Slave Address Register SAR I2C_SAR I2CSAR I2C_SAR 0xF242 Data Buffer & Comm
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Clear Receive Done Interrupt Register Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End CLRRXDONE I2C_CLR_RXDONE I2C_CLR_RXDONE 0xF2AC CLRACT I2C_CLRACTIVITY I2C_CLRACTIVITY 0xF2AE Clear Stop Detect Interrupt Register CLRSTPDET I2C_CLR_STOPDET I2C_CLR_STOPDET 0xF2B0 Clear Start Detect Interrupt Register CLRSTDET I2C_CLR_STAR_DET
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