Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

98 Freescale Semiconductor

Figure 6-22 Overall Control of Signal Source using SIM_IPSn Control

IPSn settings should not be altered while an affected peripheral is in an enabled (operational)

configuration. See the 56F802X and 56F803X Peripheral Reference Manual for details.

Figure 6-23 Internal Peripheral Source Select Register for PWM (SIM_IPS0)

6.3.19.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

6.3.19.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)—Bit 13

This field selects the alternate input source signal to feed PWM input FAULT2.

• 0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default)

• 1 = CMPBO (Internal) - Use Comparator B Output

6.3.19.3 Reserved—Bit 12

This bit field is reserved. It must be set to 0.

6.3.19.4 Select Peripheral Input Source for FAULT1 (IPS0_FAULT1)—Bit 11

This field selects the alternate input source signal to feed PWM input FAULT1.

• 0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default)

• 1 = CMPAO (Internal) - Use Comparator A Output

Base + $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0

IPS0_

FAULT2

IPS0_

FAULT1

0 0

IPS0_PSRC2 IPS0_PSRC1 IPS0_PSRC0

Write

RESET

00 0 0 0 00000000000

GPIOA5_PEREN

GPIOA5

GPIOA5 pin

SIM_IPS0

PWM

FAULT2

Comparator A

Output (Internal)

PWM5

Timer A3

SIM_GPSA0