Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
90 Freescale Semiconductor
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2
Each bit controls clocks to the indicated peripheral.
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.13 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.12 Stop Disable Register 1 (SD1)
See Section 6.3.11 for general information about Stop Disable Registers.
Figure 6-13 Stop Disable Register 1 (SD1)
6.3.12.1 Reserved—Bit 15-13
This bit field is reserved. Each bit must be set to 0.
6.3.12.2 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.3 Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
6.3.12.4 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.5 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2
• 0 = The clock is disabled during Stop mode
Base + $F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0
PIT0_
SD
0 0 0 0 0 0 0 0
TA3_
SD
TA2_
SD
TA1_
SD
TA0_
SD
Write
RESET
000 0000000000000