Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
88 Freescale Semiconductor
6.3.10.4 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3
• 0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)
• 1 = The clock is enabled to the Timer A3 module
6.3.10.5 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2
• 0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)
• 1 = The clock is enabled to the Timer A2 module
6.3.10.6 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1
• 0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)
• 1 = The clock is enabled to the Timer A1 module
6.3.10.7 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0
• 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
• 1 = The clock is enabled to the Timer A0 module
6.3.11 Stop Disable Register 0 (SD0)
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This
register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the
system to return to Run mode, this feature is provided so that selected peripherals can be left operating in
Stop mode for the purpose of generating a wake-up interrupt.
For power-conscious applications, it is recommended that only a minimum set of peripherals be
configured to remain operational during Stop mode.
Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless
their corresponding Stop Disable control is set to 1. Refer to the 56F802X and 56F803X Peripheral
Reference Manual for further details. Reads and writes cannot be made to a module that has its clock
disabled.
Figure 6-12 Stop Disable Register 0 (SD0)
6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)—Bit 15
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
CMPB_
SD
CMPA_
SD
DAC1
_SD
DAC0_
SD
0
ADC_
SD
0 0 0
I2C_
SD
0
QSCI0_
SD
0
QSPI0_
SD
0
PWM_
SD
Write
RESET
0 0 0 0 0000000 0 0 0 0 0