Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
86 Freescale Semiconductor
Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks
will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register
is set to 1.
Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)
6.3.9.1 Comparator B Clock Enable (CMPB)—Bit 15
• 0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)
• 1 = The clock is enabled to the Comparator B module
6.3.9.2 Comparator A Clock Enable (CMPA)—Bit 14
• 0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)
• 1 = The clock is enabled to the Comparator A module
6.3.9.3 Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13
• 0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)
• 1 = The clock is enabled to the DAC1 module
6.3.9.4 Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12
• 0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)
• 1 = The clock is enabled to the DAC0 module
6.3.9.5 Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.9.6 Analog-to-Digital Converter Clock Enable (ADC)—Bit 10
• 0 = The clock is not provided to the ADC module (the ADC module is disabled)
• 1 = The clock is enabled to the ADC module
6.3.9.7 Reserved—Bits 9–7
This bit field is reserved. Each bit must be set to 0.
6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6
• 0 = The clock is not provided to the I
2
C module (the I
2
C module is disabled)
• 1 = The clock is enabled to the I
2
C module
Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
CMPB CMPA DAC1 DAC0
0
ADC
0 0 0
I2C
0
QSCI0
0
QSPI0
0
PWM
Write
RESET
0 0 0 0 000 0 00 0 0 0 00 0