Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 85

peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,

if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be

available. This register is used to enable high-speed clocking for those peripherals that support it.

Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be

disabled before a peripheral clock is reconfigured.

Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)

6.3.8.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14

This bit selects the clock speed for the Quad Timer A module.

• 0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)

• 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13

This bit selects the clock speed for the PWM module.

• 0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)

• 1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.4 Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12

This bit selects the clock speed for the I

C run clock.

•0 = I

C module run clock rate equals the system clock rate, to a maximum 32MHz (default)

•1 = I

C module run clock rate equals 3X system clock rate, to a maximum 96MHz

6.3.8.5 Reserved—Bits 11–0

This bit field is reserved. Each bit must be set to 0.

6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0)

The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings

feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.

When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has

its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock

is shut off. IPBus writes are not possible.

Base + $B

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

TMRA_

PWM_

I2C_

0 0 0 0 0 0 0 0 0 0 0 0

Write

RESET

0 0 0000 0 000000000