Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
82 Freescale Semiconductor
6.3.2.7 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1,
SIM_SWC2, and SIM_SWC3)
These registers are general-purpose registers. They are reset only at power-on, so they can monitor
software execution flow.
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)
6.3.3.1 Software Control Register 0 - 3 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to
contain data that will be unaffected by the other reset sources (external reset, software reset, and COP
reset).
6.3.4 Most Significant Half of JTAG ID (SIM_MSHID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
6.3.5 Least Significant Half of JTAG ID (SIM_LSHID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$801D.
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
Base + $2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
Software Control Data 0 - 3
Write
RESET
0 0 0 0 0 0 00000 0 0000
Base + $6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 01111 1 0010
Write
RESET
0 0 0 0 0 0 01111 1 0010
Base + $7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
1 0 0 0 0 0 00000 1 1101
Write
RESET
1 0 0 0 0 0 00000 1 1101