Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
80 Freescale Semiconductor
Figure 6-1 SIM Register Map Summary
6.3.1 SIM Control Register (SIM_CTRL)
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1 Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
6.3.1.2 OnCE Enable (ONCEEBL)—Bit 5
• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled
Note: Using default state “0” is recommended.
6.3.1.3 Software Reset (SWRST)—Bit 4
• Writing 1 to this field will cause the device to reset
• Read is zero
6.3.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2
• 00 = Stop mode will be entered when the 56800E core executes a STOP instruction
• 01 = The 56800E STOP instruction will not cause entry into Stop mode
• 10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
• 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.5 Wait Disable (WAIT_DISABLE)—Bits 1–0
• 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
• 01 = The 56800E WAIT instruction will not cause entry into Wait mode
• 10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
• 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
Reserved
0 = Read as 0 1 = Read as 1 = Reserved
Base + $0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0000000000000000