Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
76 Freescale Semiconductor
5.6.19.5 Reserved—Bits 4-2
This bit field is reserved. Each bit must be set to 1.
5.6.19.6 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1 General
5.7.2 Description of Reset Operation
5.7.2.1 Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-22.
Figure 5-22 Reset Interface
5.7.3 ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
• Illegal Instruction
• SW Interrupt 3
• HW Stack Overflow
• Misaligned Long Word Access
• SW Interrupt 2
• SW Interrupt 1
• SW Interrupt 0
Table 5-5 Reset Summary
Reset Priority
Source
Characteristics
Core Reset RST
Core reset from the SIM
RES
CLK
VAB
PAB
RESET_VECTOR_ADR
READ_ADR