Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 75

5.6.19.1 Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

• 0 = No interrupt is being sent to the 56800E core

• 1 = An interrupt is being sent to the 56800E core

5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E

core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being

sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service

routine.

Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

• 00 = Required nested exception priority levels are 0, 1, 2, or 3

• 01 = Required nested exception priority levels are 1, 2, or 3

• 10 = Required nested exception priority levels are 2 or 3

• 11 = Required nested exception priority level is 3

5.6.19.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.

In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated

when the 56800E core jumps to a new interrupt service routine.

Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

• 0 = Normal operation (default)

• 1 = All interrupts disabled

Table 5-4 Interrupt Priority Encoding

IPIC_VALUE[1:0]

Current Interrupt

Priority Level

Required Nested

Exception Priority

00 No interrupt or SWILP Priorities 0, 1, 2, 3

01 Priority 0 Priorities 1, 2, 3

10 Priority 1 Priorities 2, 3

11 Priority 2 or 3 Priority 3