Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

70 Freescale Semiconductor

5.6.7.5 ADC B Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 5–4

This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.6 ADC A Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is

limited to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.7 Reserved—Bits 1–0

This bit field is reserved. Each bit must be set to 0.

5.6.8 Vector Base Address Register (VBA)

Figure 5-10 Vector Base Address Register (VBA)

5.6.8.1 Reserved—Bits 15–14

This bit field is reserved. Each bit must be set to 0.

5.6.8.2 Vector Address Bus (VAB) Bits 13–0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits

are determined based on the highest priority interrupt and are then appended onto VBA before presenting

the full VAB to the Core.

Base + $7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0

VECTOR_BASE_ADDRESS

Write

RESET

1. The 56F8033 resets to a value of 0 x 0000. This corresponds to reset addresses of 0 x 000000.

The 56F8023 resets to a value of 0 x 0080. This corresponds to reset addresses of 0 x 004000.

0000000 010000000