Datasheet

56F8033/56F8023 Features
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 7
1.1.4 Peripheral Circuits for 56F8033/56F8023
• One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
–PWM generator
–External GPIO
– Internal timers
– Analog comparator outputs
– ADC conversion result which compares with values of ADC high- and low-limit registers to set
PWM output
• Two independent 12-bit Analog-to-Digital Converters (ADCs)
— 2 x 3 channel inputs
— Supports both simultaneous and sequential conversions
— ADC conversions can be synchronized by both PWM and timer modules
— Sampling rate up to 2.67MSPS
— 16-word result buffer registers
• Two internal 12-bit Digital-to-Analog Converters (DACs)
—2 μs settling time when output swing from rail to rail
— Automatic waveform generation generates square, triangle and sawtooth waveforms with
programmable period, update rate, and range
• One 16-bit multi-purpose Quad Timer module (TMR)
— Up to 96MHz operating clock
— Eight independent 16-bit counter/timers with cascading capability
— Each timer has capture and compare capability
— Up to 12 operating modes
• One Queued Serial Communication Interface (QSCI) with LIN Slave functionality
— Full-duplex or single-wire operation
— Two receiver wake-up methods:
– Idle line
– Address mark
— Four-bytes-deep FIFOs are available on both transmitter and receiver
• One Queued Serial Peripheral Interfaces (QSPI)
— Full-duplex operation