Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 69

5.6.6.5 Reserved—Bits 7–0

This bit field is reserved. Each bit must be set to 0.

5.6.7 Interrupt Priority Register 6 (IPR6)

Figure 5-9 Interrupt Priority Register 6 (IPR6)

5.6.7.1 Reserved—Bits 15–12

This bit field is reserved. Each bit must be set to 0.

5.6.7.2 PWM Fault Interrupt Priority Level (PWM_F IPL)—Bits 11–10

This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)—Bits 9–8

This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited

to priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

5.6.7.4 ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6

This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to

priorities 0 through 2. It is disabled by default.

• 00 = IRQ disabled (default)

• 01 = IRQ is priority level 0

• 10 = IRQ is priority level 1

• 11 = IRQ is priority level 2

Base + $6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0 0 0

PWM_F IPL PWM_RL IPL ADC_ZC IPL

ADCB_CC

IPL

ADCA_CC

IPL

0 0

Write

RESET

0000000000000000