Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
66 Freescale Semiconductor
5.6.5 Interrupt Priority Register 4 (IPR4)
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.5.2 Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.5.3 Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
Base + $4
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL I2C_TX IPL I2C_RX IPL I2C_GEN IPL
Write
RESET
0000000000000000