Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
62 Freescale Semiconductor
5.6.2 Interrupt Priority Register 1 (IPR1)
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14
This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0
through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.2.2 Reserved—Bits 13–6
This bit field is reserved. Each bit must be set to 0.
5.6.2.3 FM Command, Data, Address Buffers Empty Interrupt Priority Level
(FM_CBE IPL)—Bits 5–4
This field is used to set the interrupt priority level for the FM Command, Data Address Buffers Empty
IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.2.4 FM Command Complete Interrupt Priority Level (FM_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for the FM Command Complete IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
Base + $1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
GPIOD IPL
0 0 0 0 0 0 0 0
FM_CBE IPL FM_CC IPL FM_ERR IPL
Write
RESET
00000000 0 0000000