Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
6 Freescale Semiconductor
Part 1 Overview
1.1 56F8033/56F8023 Features
1.1.1 Digital Signal Controller Core
• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2 Difference Between Devices
Table 1-1 outlines the key differences between the 56F8033 and 56F8023 devices.
1.1.3 Memory
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
•On-chip memory
— 64KB of Program Flash (56F80233 device)
32KB of Program Flash (56F8023 device)
— 8KB of Unified Data/Program RAM (56F8033 device)
4KB of Unified Data/Program RAM (56F8023 device)
• EEPROM emulation capability using Flash
Table 1-1 Device Differences
On-Chip Memory 56F8033 56F8023
Program Flash (PFLASH) 64KB 32KB
Unified RAM (RAM) 8KB 4KB