Datasheet

Block Diagram
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 57
5.4 Block Diagram
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
• Functional Mode
The ITCN is in this mode by default.
• Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
Priority
Level
2 -> 4
Decode
INT1
Priority
Level
2 -> 4
Decode
INT64
Level 0
64 -> 6
Priority
Encoder
any0
Level 3
64 -> 6
Priority
Encoder
any3
INT
VAB
IPIC
CONTROL
6
6
PIC_EN
IACK
SR[9:8]