Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

54 Freescale Semiconductor

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to

the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to

service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

• Programmable priority levels for each IRQ

• Two programmable Fast Interrupts

• Notification to SIM module to restart clocks out of Wait and Stop modes

• Ability to drive initial address on the address bus after reset

Table 4-29 Flash Module Registers Address Map

(FM_BASE = $00 F400)

FM_CLKDIV $0 Clock Divider Register

FM_CNFG $1 Configuration Register

$2 Reserved

FM_SECHI $3 Security High Half Register

FM_SECLO $4 Security Low Half Register

$5 - $9 Reserved

FM_PROT $10 Protection Register

$11 - $12 Reserved

FM_USTAT $13 User Status Register

FM_CMD $14 Command Register

$15 - $17 Reserved

FM_DATA $18 Data Buffer Register

$19 - $A Reserved

FM_IFROPT_1 $1B Information Option Register 1

$1C Reserved

FM_TSTSIG $1D Test Array Signature Register