Datasheet

Peripheral Memory-Mapped Registers

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 51

Table 4-23 Digital-to-Analog Converter 0 Registers Address Map

(DAC0_BASE = $00 F1C0)

DAC0_CTRL $0 Control Register

DAC0_DATA $1 Data Register

DAC0_STEP $2 Step Register

DAC0_MINVAL $3 Minimum Value Register

DAC0_MAXVAL $4 Maximum Value Register

Table 4-24 Comparator A Registers Address Map

(CMPA_BASE = $00 F1E0)

CMPA_CTRL $0 Control Register

CMPA_STAT $1 Status Register

CMPA_FILT $2 Filter Register

Table 4-25 Comparator B Registers Address Map

(CMPB_BASE = $00 F1F0)

CMPB_CTRL $0 Control Register

CMPB_STAT $1 Status Register

CMPB_FILT $2 Filter Register

Table 4-26 Queued Serial Communication Interface 0 Registers Address Map

(QSCI0_BASE = $00 F200)

QSCI0_RATE $0 Baud Rate Register

QSCI0_CTRL1 $1 Control Register 1

QSCI0_CTRL2 $2 Control Register 2

QSCI0_STAT $3 Status Register

QSCI0_DATA $4 Data Register