Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

50 Freescale Semiconductor

Table 4-20 GPIOD Registers Address Map

(GPIOD_BASE = $00 F180)

GPIOD_PUPEN $0 Pull-up Enable Register

GPIOD_DATA $1 Data Register

GPIOD_DDIR $2 Data Direction Register

GPIOD_PEREN $3 Peripheral Enable Register

GPIOD_IASSRT $4 Interrupt Assert Register

GPIOD_IEN $5 Interrupt Enable Register

GPIOD_IEPOL $6 Interrupt Edge Polarity Register

GPIOD_IPEND $7 Interrupt Pending Register

GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register

GPIOD_PPOUTM $9 Push-Pull Output Mode Control Register

GPIOD_RDATA $A Raw Data Input Register

GPIOD_DRIVE $B Output Drive Strength Control Register

Table 4-21 Programmable Interval Timer 0 Registers Address Map

(PIT0_BASE = $00 F190)

PIT0_CTRL $0 Control Register

PIT0_MOD $1 Modulo Register

PIT0_CNTR $2 Counter Register

Table 4-22 Digital-to-Analog Converter 0 Registers Address Map

(DAC0_BASE = $00 F1C0)

DAC0_CTRL $0 Control Register

DAC0_DATA $1 Data Register

DAC0_STEP $2 Step Register

DAC0_MINVAL $3 Minimum Value Register

DAC0_MAXVAL $4 Maximum Value Register