Datasheet

Peripheral Memory-Mapped Registers

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 47

Reserved

SIM_GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB

SIM_GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB

Reserved

SIM_ISS0 $18 Internal Source Select Register 0 for PWM

SIM_ISS1 $19 Internal Source Select Register 1 for DACs

SIM_ISS2 $1A Internal Source Select Register 2 for TMRA

Reserved

Table 4-14 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F120)

COP_CTRL $0 Control Register

COP_TOUT $1 Time-Out Register

COP_CNTR $2 Counter Register

Table 4-15 Clock Generation Module Registers Address Map

(OCCS_BASE = $00 F130)

OCCS_CTRL $0 Control Register

OCCS_DIVBY $1 Divide-By Register

OCCS_STAT $2 Status Register

Reserved

OCCS_OCTRL $5 Oscillator Control Register

OCCS_CLKCHK $6 Clock Check Register

OCCS_PROT $7 Protection Register

Table 4-16 Power Supervisor Registers Address Map

(PS_BASE = $00 F140)

PS_CTRL $0 Control Register

PS_STAT $1 Status Register

Reserved

Table 4-13 SIM Registers Address Map (Continued)

(SIM_BASE = $00 F100)