Datasheet

56F8033/56F8023 Data Sheet, Rev. 6

46 Freescale Semiconductor

ITCN_FIM0 $8 Fast Interrupt Match 0 Register

ITCN_FIVAL0 $9 Fast Interrupt Vector Address Low 0 Register

ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register

ITCN_FIM1 $B Fast Interrupt Match 1 Register

ITCN_FIVAL1 $C Fast Interrupt Vector Address Low 1 Register

ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register

ITCN_IRQP0 $E IRQ Pending Register 0

ITCN_IRQP1 $F IRQ Pending Register 1

ITCN_IRQP2 $10 IRQ Pending Register 2

ITCN_IRQP3 $11 IRQ Pending Register 3

Reserved

ITCN_ICTRL $16 Interrupt Control Register

Reserved

Table 4-13 SIM Registers Address Map

(SIM_BASE = $00 F100)

SIM_CTRL $0 Control Register

SIM_RSTAT $1 Reset Status Register

SIM_SWC0 $2 Software Control Register 0

SIM_SWC1 $3 Software Control Register 1

SIM_SWC2 $4 Software Control Register 2

SIM_SWC3 $5 Software Control Register 3

SIM_MSHID $6 Most Significant Half JTAG ID

SIM_LSHID $7 Least Significant Half JTAG ID

SIM_PWR $8 Power Control Register

Reserved

SIM_CLKOUT $A Clock Out Select Register

SIM_PCR $B Peripheral Clock Rate Register

SIM_PCE0 $C Peripheral Clock Enable Register 0

SIM_PCE1 $D Peripheral Clock Enable Register 1

SIM_SD0 $E Peripheral STOP Disable Register 0

SIM_SD1 $F Peripheral STOP Disable Register 1

SIM_IOSAHI $10 I/O Short Address Location High Register

SIM_IOSALO $11 I/O Short Address Location Low Register

SIM_PROT $12 Protection Register

SIM_GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA

Table 4-12 Interrupt Control Registers Address Map (Continued)

(ITCN_BASE = $00 F0E0)