Datasheet

Peripheral Memory-Mapped Registers

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 45

PWM_OUT $3 Output Control Register

PWM_CNTR $4 Counter Register

PWM_CMOD $5 Counter Modulo Register

PWM_VAL0 $6 Value Register 0

PWM_VAL1 $7 Value Register 1

PWM_VAL2 $8 Value Register 2

PWM_VAL3 $9 Value Register 3

PWM_VAL4 $A Value Register 4

PWM_VAL5 $B Value Register 5

PWM_DTIM0 $C Dead Time Register 0

PWM_DTIM1 $D Dead Time Register 1

PWM_DMAP1 $E Disable Mapping Register 1

PWM_DMAP2 $F Disable Mapping Register 2

PWM_CNFG $10 Configure Register

PWM_CCTRL $11 Channel Control Register

PWM_PORT $12 Port Register

PWM_ICCTRL $13 Internal Correction Control Register

PWM_SCTRL $14 Source Control Register

PWM_SYNC $15 Synchronization Window Register

PWM_FFILT0 $16 Fault0 Filter Register

PWM_FFILT1 $17 Fault1 Filter Register

PWM_FFILT2 $18 Fault2 Filter Register

PWM_FFILT3 $19 Fault3 Filter Register

Table 4-12 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F0E0)

ITCN_IPR0 $0 Interrupt Priority Register 0

ITCN_IPR1 $1 Interrupt Priority Register 1

ITCN_IPR2 $2 Interrupt Priority Register 2

ITCN_IPR3 $3 Interrupt Priority Register 3

ITCN_IPR4 $4 Interrupt Priority Register 4

ITCN_IPR5 $5 Interrupt Priority Register 5

ITCN_IPR6 $6 Interrupt Priority Register 6

ITCN_VBA $7 Vector Base Address Register

Table 4-11 Pulse Width Modulator Registers Address Map (Continued)

(PWM_BASE = $00 F0C0)