Datasheet

Peripheral Memory-Mapped Registers

56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor 43

TMRA3_SCTRL $37 Status and Control Register

TMRA3_CMPLD1 $38 Comparator Load Register 1

TMRA3_CMPLD2 $39 Comparator Load Register 2

TMRA3_CSCTRL $3A Comparator Status and Control Register

TMRA3_FILT $3B Input Filter Register

Reserved

Table 4-10 Analog-to-Digital Converter Registers Address Map

(ADC_BASE = $00 F080)

ADC_CTRL1 $0 Control Register 1

ADC_CTRL2 $1 Control Register 2

ADC_ZXCTRL $2 Zero Crossing Control Register

ADC_CLIST 1 $3 Channel List Register 1

ADC_CLIST 2 $4 Channel List Register 2

ADC_CLIST 3 $5 Channel List Register 3

ADC_CLIST 4 $6 Channel List Register 4

ADC_SDIS $7 Sample Disable Register

ADC_STAT $8 Status Register

ADC_RDY $9 Conversion Ready Register

ADC_LIMSTAT $A Limit Status Register

ADC_ZXSTAT $B Zero Crossing Status Register

ADC_RSLT0 $C Result Register 0

ADC_RSLT1 $D Result Register 1

ADC_RSLT2 $E Result Register 2

ADC_RSLT3 $F Result Register 3

ADC_RSLT4 $10 Result Register 4

ADC_RSLT5 $11 Result Register 5

ADC_RSLT6 $12 Result Register 6

ADC_RSLT7 $13 Result Register 7

ADC_RSLT8 $14 Result Register 8

ADC_RSLT9 $15 Result Register 9

ADC_RSLT10 $16 Result Register 10

ADC_RSLT11 $17 Result Register 11

ADC_RSLT12 $18 Result Register 12

ADC_RSLT13 $19 Result Register 13

Table 4-9 Quad Timer A Registers Address Map (Continued)

(TMRA_BASE = $00 F000)