Datasheet
56F8033/56F8023 Data Sheet, Rev. 6
42 Freescale Semiconductor
TMRA0_FILT $B Input Filter Register
Reserved
TMRA0_ENBL $F Timer Channel Enable Register
TMRA1_COMP1 $10 Compare Register 1
TMRA1_COMP2 $11 Compare Register 2
TMRA1_CAPT $12 Capture Register
TMRA1_LOAD $13 Load Register
TMRA1_HOLD $14 Hold Register
TMRA1_CNTR $15 Counter Register
TMRA1_CTRL $16 Control Register
TMRA1_SCTRL $17 Status and Control Register
TMRA1_CMPLD1 $18 Comparator Load Register 1
TMRA1_CMPLD2 $19 Comparator Load Register 2
TMRA1_CSCTRL $1A Comparator Status and Control Register
TMRA1_FILT $1B Input Filter Register
Reserved
TMRA2_COMP1 $20 Compare Register 1
TMRA2_COMP2 $21 Compare Register 2
TMRA2_CAPT $22 Capture Register
TMRA2_LOAD $23 Load Register
TMRA2_HOLD $24 Hold Register
TMRA2_CNTR $25 Counter Register
TMRA2_CTRL $26 Control Register
TMRA2_SCTRL $27 Status and Control Register
TMRA2_CMPLD1 $28 Comparator Load Register 1
TMRA2_CMPLD2 $29 Comparator Load Register 2
TMRA2_CSCTRL $2A Comparator Status and Control Register
TMRA2_FILT $2B Input Filter Register
Reserved
TMRA3_COMP1 $30 Compare Register 1
TMRA3_COMP2 $31 Compare Register 2
TMRA3_CAPT $32 Capture Register
TMRA3_LOAD $33 Load Register
TMRA3_HOLD $34 Hold Register
TMRA3_CNTR $35 Counter Register
TMRA3_CTRL $36 Control Register
Table 4-9 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F000)
Register Acronym Address Offset Register Description