Datasheet

Peripheral Memory-Mapped Registers
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 41
Table 4-8 Data Memory Peripheral Base Address Map Summary
Peripheral Prefix Base Address Table Number
Timer A TMRA X:$00 F000 4-9
ADC ADC X:$00 F080 4-10
PWM PWM X:$00 F0C0 4-11
ITCN ITCN X:$00 F0E0 4-12
SIM SIM X:$00 F100 4-13
COP COP X:$00 F120 4-14
CLK, PLL, OSC OCCS X:$00 F130 4-15
Power Supervisor PS X:$00 F140 4-16
GPIO Port A GPIOA X:$00 F150 4-17
GPIO Port B GPIOB X:$00 F160 4-18
GPIO Port C GPIOC X:$00 F170 4-19
GPIO Port D GPIOD X:$00 F180 4-20
PIT 0 PIT0 X:$00 F190 4-21
DAC 0 DAC0 X:$00 F1C0 4-22
DAC 1 DAC1 X:$00 F1D0 4-23
Comparator A CMPA X:$00 F1E0 4-24
Comparator B CMPB X:$00 F1F0 4-25
QSCI 0 SCI0 X:$00 F200 4-26
QSPI 0 SPI0 X:$00 F220 4-27
I
2
C
I2C X:$00 F280 4-28
FM FM X:$00 F400 4-29
Table 4-9 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F000)
Register Acronym Address Offset Register Description
TMRA0_COMP1 $0 Compare Register 1
TMRA0_COMP2 $1 Compare Register 2
TMRA0_CAPT $2 Capture Register
TMRA0_LOAD $3 Load Register
TMRA0_HOLD $4 Hold Register
TMRA0_CNTR $5 Counter Register
TMRA0_CTRL $6 Control Register
TMRA0_SCTRL $7 Status and Control Register
TMRA0_CMPLD1 $8 Comparator Load Register 1
TMRA0_CMPLD2 $9 Comparator Load Register 2
TMRA0_CSCTRL $A Comparator Status and Control Register