Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
4 Freescale Semiconductor
56F8033/56F8023 Block Diagram
Programmable
Interval
Timer
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
4
Unified Data /
Program RAM
2K x 16
4K x 16
PDB
PDB
XAB1
XAB2
XDB2
CDBR
QSPI
or PWM
or I
2
C
or TMRA
or GPIOB
IPBus Bridge (IPBB)
System Bus
Control
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
Low-Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
4
RESET or
GPIOA
AD0
4
Clock
Generator*
System
Integration
Module
P
O
R
O
S
C
PWM
or TMRA or GPIOA
*Includes On-Chip
Relaxation Oscillator
COP/
Watchdog
AD1
4
Program Memory
16K x 16 Flash
32K x 16 Flash
ADC
or CMP
or GPIOC
QSCI
or PWM
or I
2
C
or TMRA
or GPIOB
2
2
I
2
C
or CMP
or GPIOB
2
5
DAC
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program
RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
56F8033/56F8023 General Description