Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
34 Freescale Semiconductor
Figure 3-3 Connecting an External Clock Signal using XTAL
3.8 Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock
source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary).
The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external
clock input.
Figure 3-4 Connecting an External Clock Signal using GPIO
Part 4 Memory Maps
4.1 Introduction
The 56F8033/56F8023 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is
shared by both spaces and Flash memory is used only in Program space.
This section provides memory maps for:
• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
56F8033/56F8023
External
Clock
XTAL EXTAL
GND or
GPIO
CLKMODE = 1
56F8033/56F8023
GPIO
External Clock