Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
26 Freescale Semiconductor
GPIOB2
(MISO0)
(TA2
8
)
(PSRC0)
17 Input/
Output
Input/
Output
Input/
Output
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
TA2 — Timer A, Channel 2
PSRC0 — External PWM signal source input for the complementary
PWM4/PWM5 pair.
After reset, the default state is GPIOB2. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
8
The TA2 signal is also brought out on the GPIOA4 pin.
GPIOB3
(MOSI0)
(TA3
9
)
(PSRC1)
16 Input/
Output
Input/
Output
Input/
Output
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master Out/Slave In— This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
TA3 — Timer A, Channel 3
PSRC1 — External PWM signal source input for the complementary
PWM2/PWM3 pair.
After reset, the default state is GPIOB3. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
9
The TA3 signal is also brought out on the GPIOA5 pin.
Return to Table 2-2
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description