Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
22 Freescale Semiconductor
2.2 56F8033/56F8023 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
V
DD
26 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface.
V
SS
13 Supply Supply V
SS
— These pins provide ground for chip logic and I/O drivers.
V
SS
27
V
DDA
8 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
V
SSA
9 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
V
CAP
25 Supply Supply V
CAP
— Connect this pin to a 4.7μF or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See Section 10.2.1.
RESET
(GPIOA7)
15 Input
Input/Open
Drain
Output
Input,
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET
functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET
.
GPIOA0
(PWM0)
29 Input/
Output
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
PWM0 — This is one of the six PWM output pins.
After reset, the default state is GPIOA0.
Return to Table 2-2