Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
18 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8033/56F8023 are organized into functional groups, as detailed in
Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or
signals present on a pin, sorted by pin number.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of Pins
Power Inputs (V
DD
, V
DDA
)2
Ground (V
SS
, V
SSA
)3
Supply Capacitors 1
Reset
1
1. Pins may be shared with other peripherals. See Table 2-2.
1
Pulse Width Modulator (PWM) Ports
1
11
Serial Peripheral Interface (SPI) Ports
1
4
Timer Module A (TMRA) Ports
1
4
Analog-to-Digital Converter (ADC) Ports
1
6
Serial Communications Interface 0 (SCI0) Ports
1
2
Inter-Integrated Circuit Interface (I
2
C) Ports
1
2
JTAG/Enhanced On-Chip Emulation (EOnCE
1
)
4