Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
156 Freescale Semiconductor
Transmitter Message
Abort Acknowledge
Register
TAAK CAN_TAAK CANTAAK 0XF809
Transmitter FIFO
Selection Register
TBSEL CAN_TBSEL CANTBSEL 0XF80 A
Identifier Acceptance
Control Register
IDAC CAN_IDAC CANIDAC 0XF80B
Miscellaneous
Register
MISC CAN_MISC CANMISC 0X F 80D
Receive Error
Register
RXERR CAN_RXERR CANRXERR 0XF80E
Transmit Error
Register
TXERR CAN_TXERR CANTXERR 0XF 80F
Identifier Acceptance
0-3 Registers
IDAR0-3 CAN_IDAR0-3 CANIDAR0-3 0xF810 0xF813
Identifier Mask 0-3
Registers
IDMR0-3 CAN_IDMR0-3 CANIDMR0-3 0xF 814 0xF8 17
Identifier Acceptance
4-7 Register
IDAR4-7 CAN_IDAR4-7 CANIDAR4-7 0xF818 0xF81B
Identifier Mask 4-7
Registers
IDMR4-7 CAN_IDMR4-7 CANIDMR4-7 0xF 81C 0xF 8 1F
Foreground Receive
FIFO Register
RXFG CAN_RXFG CANRXFG 0xF82F 0xF820
Foreground Transmit
FIFO Register
TXFG CAN_TXFG CANTXFG 0xF8 30 0xF83F
Power Supervisor (PS) Module
Control Register CTRL LVICONTROL PS_CTRL LVICONTROL LVICTRL 0xF140
Status Register STAT LVISTATUS PS_STAT LVISTATUS LVISR 0xF141
Queued Serial Communications Interface (QSCI) Module
n = 0, 1
Baud Rate Register RATE QSCI_RATE QSCI_SCIBR 0xF2n0
Control 1 Register CTRL1 QSCI_CTRL1 QSCI_SCICR 0xF2n1
Cont r ol 2 R e giste r CTRL2 QSCI_CTRL2 QSCI_SCICR2 0 xF2n2
Status Register STAT QSCI_STAT QSCI_SCISR 0xF2n3
Data Register DATA QSCI_DATA QSCI_SCIDR 0xF2n4
Queued Serial Peripheral Interface (QSPI) Module
Status and Control
Register
SCTRL QSPI_SCTRL QSPI_SPSCR 0xF 2n0
Data Size and Control
Register
DSCTRL QSPI_DSCTRL QSPI_SPDSR 0xF2n1
Data Receive
Register
DRCV QSPI_DRCV QSPI_SPDRR 0 xF2n2
Data Transmit
Register
DXMIT QSPI_DXMIT QSPI_SPDTR 0xF2n3
Table 14-1 Legacy and Revised Acronyms (Continued)
Register Name
Peripheral Reference
Manual
Data Sheet
Processor Expert
Acronym
Memory
Address
New
Acronym
Legacy
Acronym
New
Acronym
Legacy
Acronym
Start End