Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
152 Freescale Semiconductor
Inter-Integrated Circuit Interface (I
2
C) Module
Cont r ol Re g ister CTRL IBCR I2C_CTRL I2C_IBCR I2C_IBCR 0x F280
Target Address
Register
TAR I2C_TAR I2CTAR I2C_TAR 0xF282
Slave Address
Register
SAR I2C_SAR I2CSAR I2C_SAR 0xF 2 42
Data Buffer &
Command Register
DATA I2C_DATA I2C_DATACMD I2C_DATACMD 0xF288
Standard Speed
Clock SCL High
Count Register
SSHCNT I2C_SS_SCL_HCNT I2C_SS_SCLHCNT I2C_SS_SCLHCNT 0xF28 A
Standard Speed
Clock SCL Low Count
Register
SSLCNT I2C_SS_SCL_LCNT I2C_SS_SCLLCNT I2C_SS_SCLLCNT 0xF28C
Fast Speed Clock
SCL High Count
Register
FSHCNT I2C_FS_SCL_HCNT I2C_FS_SCLHCNT I2C_FS_SCLHCNT 0 xF28E
Fast Speed Clock
SCL Low Count
Register
FSLCNT I2C_FS_SCL_LCNT I2C_FS_SCLLCNT I2C_FS_SCLLCNT 0xF290
Interrupt Status
Register
ISTAT I2C_INTR_STAT I2C_INTRSTAT I2C_INTRSTAT 0x F296
Interrupt Mask
Register
IENBL I2C_INTR_MASK I2C_INTRMASK I2C_INTRMASK 0xF298
Raw Interrupt Status
Register
RISTAT I2C_RAW_INTR_ STAT I2C_RAW_INTRSTAT I2C_RAW_INTRSTAT 0xF29 A
Receive FIFO
Threshold Level
Register
RXFT I2C_RXTL I2C_RXTL 0xF2 9C
Transmit FIFO
Threshold Level
Register
TXFT I2C_TXTL I2C_TXTL 0xF29E
Clear Combined &
Individual Interrupts
Register
CLRINT I2C_CLRINTR I2C_CLRINTR 0 x F2A0
Clear Receive Under
Interrupt Register
CLRRXUND I2C_CLR_RXUNDER I2C_CLR_RXUNDER 0xF2A2
Clear Receive Over
Interrupt Register
CLRRXOVR I2C_CLROVER I2C_CLROVER 0xF2 A 4
Clear Transmit Over
Register
CLRTXOVR I2C_CLR_TXOVER I2C_CLR_TXOVER 0xF2A6
Clear Read Required
Interrupt Register
CLRRDREQ I2C_CLR_RDREQ I2C_CLR_RDREQ 0xF2 A8
Clear Transmit Abort
Interrupt Register
CLRTXABRT I2C_CLR_TXABRT I2C_CLR_TXABRT 0xF2AA
Table 14-1 Legacy and Revised Acronyms (Continued)
Register Name
Peripheral Reference
Manual
Data Sheet
Processor Expert
Acronym
Memory
Address
New
Acronym
Legacy
Acronym
New
Acronym
Legacy
Acronym
Start End