Datasheet

Electrical Design Considerations
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 149
• Take special care to minimize noise levels on the V
REF
, V
DDA
, and V
SSA
pins
• Using separate power planes for V
DD
and V
DDA
and separate ground planes for V
SS
and V
SSA
are
recommended. Connect the separate analog and digital power and ground planes as close as possible to
power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is
advisable to connect a small inductor or ferrite bead in serial with both V
DDA
and V
SSA
traces.
• It is highly desirable to physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the Flash memory is programmed through the JTAG/EOnCE port, QSPI, QSCI, or I
2
C, the
designer should provide an interface to this port if in-circuit Flash programming is desired.
• If desired, connect an external RC circuit to the R
ESET pin. The Resistor value should be in the range of
4.7k—10k; the Capacitor value should be in the range of 0.22µf - 4.7µf.
• Add a 3.3k external pull-up on the TMS pin of the JTAG port to keep EOnce in a restate during normal
operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pull-up
enable. The typical value of internal pull-up is around 110K. These internal pull-ups can be disabled by
software.
• To eliminate PCB trace impedance effect, each ADC input should have a 33pf-10 ohm RC filter.
• Device GPIOs have only a down (substrate) diode on the GPIO circuit. Devices do not have a positive clamp
diode because GPIOs use a floating gate structure to tolerate 5V input. The absolute maximum clamp
current is -20mA at V
in
less than 0V. The continuous clamp current is -2mA at V
in
less than 0V. If positive
voltage spikes are a concern, a positive clamp is recommended.
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order devices.
* This package is RoHS compliant.
Table 13-1 56F8033/56F8023 Ordering Information
Device
Supply
Voltage
Package Type
Pin
Count
Frequency
(MHz)
Ambient
Temperature
Range
Order Number
MC56F8033 3.0–3.6 V
Low-Profile Quad Flat Pack (LQFP)
32 32 -40° to + 105° C MC56F8033VLC*
MC56F8023 3.0–3.6 V
Low-Profile Quad Flat Pack (LQFP)
32 32 -40° to + 105° C MC56F8023VLC*