Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
138 Freescale Semiconductor
10.15 Equivalent Circuit for ADC Inputs
Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample
and hold circuit moves to (V
REFHx
- V
REFLx
) / 2, while the other charges to the analog input voltage. When
the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V
REFHx
-V
REFLx
) / 2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
REF
, and the ADC clock frequency.
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
3. Equivalent resistance for the channel select mux; 100 ohms
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
Figure 10-17 Equivalent Circuit for A/D Loading
10.16 Comparator (CMP) Parameters
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC.
Table 10-20 CMP Parameters
Characteristic Conditions/Comments Symbol Min Typ Max Unit
Input Offset Voltage
1
Within range of V
DDA
- .1V to
V
SSA
+ .1V
V
OFFSET
— ± 10 ± 35 mV
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(V
REFHx
- V
REFLx
) / 2
125Ω ESD Resistor
8pF noise damping capacitor