Datasheet

JTAG Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 135
Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I
2
C Bus
10.13 JTAG Timing
Figure 10-15 Test Clock Input Timing Diagram
Table 10-18 JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK frequency of operation
1
1. TCK frequency of operation must be less than 1/8 the processor rate.
f
OP
DC SYS_CLK/8 MHz 10-15
TCK clock pulse width
t
PW
50 — ns 10-15
TMS, TDI data set-up time
t
DS
5—ns 10-16
TMS, TDI data hold time
t
DH
5—ns 10-16
TCK low to TDO data valid
t
DV
—30ns 10-16
TCK low to TDO tri-state
t
TS
—30ns 10-16
SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
t
PW
1/f
OP
t
PW
V
M
V
IH