Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
134 Freescale Semiconductor
10.12 Inter-Integrated Circuit Interface (I
2
C) Timing
Table 10-17 I
2
C Timing
Characteristic Symbol
Standard Mode Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
01000400kHz
Hold time (repeated)
START condition. After
this period, the first clock
pulse is generated.
t
HD; STA
4.0 — 0.6 — μs
LOW period of the SCL
clock
t
LOW
4.7 — 1.3 — μs
HIGH period of the SCL
clock
t
HIGH
4.0 — 0.6 — μs
Set-up time for a repeated
START condition
t
SU; STA
4.7 — 0.6 — μs
Data hold time for I
2
C bus
devices
t
HD; DAT
0
1
1. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.45
2
2. The maximum t
HD; DAT
must be met only if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
0
1
0.9
2
μs
Data set-up time t
SU; DAT
250
3
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
—
100
3, 4
4. A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement t
SU; DAT
> = 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250ns (according to the Standard mode I
2
C bus specification) before the SCL line is
released.
—ns
Rise time of both SDA and
SCL signals
t
r
— 1000
20 +0.1C
b
5
5. C
b
= total capacitance of the one bus line in pF.
300 ns
Fall time of both SDA and
SCL signals
t
f
—300
20 +0.1C
b
5
300 ns
Set-up time for STOP
condition
t
SU; STO
4.0 — 0.6 — μs
Bus free time between
STOP and START
condition
t
BUF
4.7 — 1.3 — μs
Pulse width of spikes that
must be suppressed by
the input filter
t
SP
N/A N/A 0 50 ns