Datasheet

Serial Peripheral Interface (SPI) Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 129
Figure 10-7 SPI Master Timing (CPHA = 0)
1. Parameters listed are guaranteed by design.
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
t
F
t
C
t
CL
t
CL
t
R
t
R
t
F
t
DS
t
DH
t
CH
t
DI
t
DV
t
DI
(ref)
t
R
Master MSB out Bits 14–1 Master LSB out
SS
(Input)
t
CH
SS is held High on master
t
F