Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
128 Freescale Semiconductor
10.9 Serial Peripheral Interface (SPI) Timing
Table 10-14 SPI Timing
1
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
125
62.5
—
—
ns
ns
10-7, 10-8,
10-9, 10-10
Enable lead time
Master
Slave
t
ELD
—
31
—
—
ns
ns
10-10
Enable lag time
Master
Slave
t
ELG
—
125
—
—
ns
ns
10-10
Clock (SCK) high time
Master
Slave
t
CH
50
31
—
—
ns
ns
10-7, 10-8,
10-9, 10-10
Clock (SCK) low time
Master
Slave
t
CL
50
31
—
—
ns
ns
10-10
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
10-7, 10-8,
10-9, 10-10
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
10-7, 10-8,
10-9, 10-10
Access time (time to data active from
high-impedance state)
Slave
t
A
4.8 15 ns
10-10
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
10-10
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
10-7, 10-8,
10-9, 10-10
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
10-7, 10-8,
10-9, 10-10
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
10-7, 10-8,
10-9, 10-10
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
10-7, 10-8,
10-9, 10-10