Datasheet

Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 127
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = system clock cycle and T
osc
= oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At
8MHz (used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Typical Min Typical Max Unit See Figure
Minimum RESET
Assertion Duration
t
RA
4T — ns —
Minimum GPIO pin Assertion for Interrupt
t
IW
2T — ns 10-6
RESET
deassertion to First Address Fetch
3
3. During Power-On Reset, it is possible to use the 56F8033/56F8023 internal reset stretching circuitry to extend this period to
2^21T.
t
RDA
96T
OSC
+ 64T 97T
OSC
+ 65T ns —
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
t
IF
—6Tns—
GPIO pin
(Input)
T
IW