Datasheet

Phase Locked Loop Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor 125
10.6 Phase Locked Loop Timing
10.7 Relaxation Oscillator Timing
Table 10-11 PLL Timing
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
f
osc
48—MHz
Internal reference relaxation oscillator frequency for the PLL
f
rosc
—8—MHz
PLL output frequency
2
(24 x reference frequency)
2. The core system clock will operate at 1/6 of the PLL output frequency.
f
op
96 192 — MHz
PLL lock time
3
3. This is the time required after the PLL is enabled to ensure reliable operation.
t
plls
—40100µs
Accumulated jitter using an 8MHz external crystal as the PLL source
4
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
J
A
— — 0.37 %
Cycle-to-cycle jitter
t
jitterpll
—350—ps
Table 10-12 Relaxation Oscillator Timing
Characteristic Symbol Minimum Typical Maximum Unit
Relaxation Oscillator output frequency
1
Normal Mode
Standby Mode
1. Output frequency after factory trim.
f
op
—
8.05
200
—
MHz
kHz
Relaxation Oscillator stabilization time
2
2. This is the time required from Standby to Normal mode transition.
t
roscs
—1 3ms
Cycle-to-cycle jitter. This is measured on the CLKO
signal (programmed prescaler_clock) over 264 clocks
3
3. J
A
is required to meet QSCI requirements.
t
jitterrosc
—400— ps
Minimum tuning step size — .08 — %
Maximum tuning step size — 40 — %
Variation over temperature -40°C to 150ºC
4
— +1.0 to -1.5 +3.0 to -3.0 %
Variation over temperature 0°C to 105ºC
4
— 0 to +1 +2.0 to -2.0 %