Datasheet

56F8033/56F8023 Data Sheet, Rev. 6
10 Freescale Semiconductor
2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0
and Timer Channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register;
see Section 6.3.1.
Figure 1-1 56800E Core Block Diagram
Data
DSP56800E Core
Arithmetic
Logic Unit
(ALU)
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Program
Memory
Data /
IPBUS
Interface
Bit-
Manipulation
Unit
N3
M01
Address
XAB1
Generation
Unit
(AGU)
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
FISR
LC
LC2
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Program Control Unit
ALU1 ALU2
MAC and ALU
A1A2 A0
B1B2 B0
C1C2 C0
D1D2 D0
Y1
Y0
X0
Enhanced
JTAG TAP
R2
R3
R4
R5
SP
R0
R1
N
Y
Multi-Bit Shifter
OnCE™
Program
RAM