56F8033/56F8023 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8023 Rev. 6 02/2010 freescale.
Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz.
Document Revision History Version History Rev. 6 Description of Change In the table Recommended Operating Conditions, removed the line “XTAL not driven by an external clock“ from the characteristic “Oscillator Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source” Added 56F8033 device to document Removed “Preliminary” from data sheet In the System Integration Module (SIM) chapter, fixed typos Please see http://www.freescale.
56F8033/56F8023 General Description • Up to 32 MIPS at 32MHz core frequency • One Programmable Interval Timer (PIT) • DSP and MCU functionality in a unified, C-efficient architecture • One Queued Serial Communication Interface (QSCI) with LIN slave functionality • 56F8033 offers 64KB (32K x 16) Program Flash • One Queued Serial Peripheral Interfaces (QSPI) • 56F8023 offers 32KB (16K x 16) Program Flash • One 16-bit Quad Timer • 56F8033 offers 8KB (4K x 16) Unified Data/Program RAM • One Inter-Integ
6F8033/56F8023 Data Sheet Table of Contents Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 56F8033/56F8023 Features . . . . . . . . . . . 6 56F8033/56F8023 Description . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 9 Architecture Block Diagram . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . 17 Data Sheet Conventions . . . . . . . . . . . . . 17 7.3 Product Analysis. . . . . . . . . . . . .
Part 1 Overview 1.1 56F8033/56F8023 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8033/56F8023 Features 1.1.
— Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions (2 to 16 bits) • One Inter-Integrated Circuit (I2C) port — Operates up to 400kbps — Supports both master and slave operation — Supports both 10-bit address mode and broadcasting mode • • One 16-bit Programmable Interval Timer (PIT) Two analog Comparators (CMPs) — Selectable input source includes external pins, DACs — Programmable output polarity — Output can drive Timer input, PW
Award-Winning Development Environment The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.
2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0 and Timer Channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register; see Section 6.3.1.
Architecture Block Diagram To/From IPBus Bridge OCCS (ROSC / PLL / OSC) Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM GPIO D RESET (Muxed with GPIOA7) COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8033/56F8023 Data Sheet, Rev.
To/From IPBus Bridge INTC SYNC DAC SYNC on Figure 1-5 PIT0 2 3 Sync0, Sync1 Over/Under Limits SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on Figure 1-5 GPIOC2 ANA2 (VREFHA) GPIOC1 ANA1 ADC ANB0 ANB0 on Figure 1-5 GPIOC6 ANB2 (VREFHB) GPIOC5 ANB1 IPBus Figure 1-3 56F8033/56F8023 I/O Pin-Out Muxing (Part 1/5) 56F8033/56F8023 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge CLKO GPIOB4 TA0 on Figure 1-7 GPIOB6 - 7 QSCI0 RXD0, TXD0 2 TA2, TA3 on Figure 1-7 GPIOB2 - 3 MISO0, MOSI0 QSPI0 SCLK0, SS0 2 2 2 I2C SCL, SDA 2 GPIOB0 - 1 2 IPBus Figure 1-4 56F8033/56F8023 I/O Pin-Out Muxing (Part 2/5) 56F8033/56F8023 Data Sheet, Rev.
To/From IPBus Bridge CMP_IN3 CMPAI3 GPIOC0 CMPA CMP_OUT CMPAO on Figure 1-6, Figure 1-7 Export Import ANA0 on Figure 1-3 DAC0 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 2 TA0o, TA1o on Figure 1-7 DAC1 ANB0 on Figure 1-3 Import Export CMP_OUT CMPBO on Figure 1-6, Figure 1-7 CMPB GPIOC4 CMP_IN3 CMPBI3 IPBus Figure 1-5 56F8033/56F8023 I/O Pin-Out Muxing (Part 3/5) 56F8033/56F8023 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge TA0 on Figure 1-7 GPIOA6 2 TA2 - 3 on Figure 1-7 GPIOA0 - 3 4 PWM0 - 3 FAULT0 2 PWMA4 - 5 1 GPIOA4 - 5 2 PWM FAULT1 FAULT2 RELOAD PSRC0 - 2 1 FAULT3 TA1 on Figure 1-7 GPIOB5 RELOAD on Figure 1-7, Figure 1-5 IPBus CMPAO on Figure 1-5 CMPBO on Figure 1-5 3 3 3 3 GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3 Figure 1-6 56F8033/56F8023 I/O Pin-Out Muxing (Part 4/5) 56F8033/56F8023 Data Sheet, Rev.
To/From IPBus Bridge TA0o on Figure 1-6 (PWM) T0o T0i TA0 on Figure 1-6 (GPIOA6) TA0 on Figure 1-4 (GPIOB4) T1o T1i TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TMRA TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o T2i TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) T3o T3i TA3 on Figure 1-4 (GPIOB3) RELOAD on Figure 1-6 (PWM) IPBus Figure 1-7 56F8033/56F8023 I/O Pin-Out M
Product Documentation 1.5 Product Documentation The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8033/56F8023. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8033/56F8023 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number.
Introduction In Table 2-2, peripheral pins in bold identify reset state.
Table 2-2 56F8033/56F8023 Pins (Continued) Peripherals: Pin # Pin Name 29 GPIOA0 GPIOA0, PWM0 A0 30 TDI TDI, GPIOD0 D0 TD1 31 TMS TMS, GPIOD3 D3 TMS 32 TDO TDO, GPIOD1 D1 TDO Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer Comp Power & Ground JTAG Misc. PWM0 56F8033/56F8023 Data Sheet, Rev.
Introduction VDD Power VSS Ground VDDA Power VSSA Ground Other Supply Ports VCAP RESET or GPIOA RESET (GPIOA7) 1 2 1 1 4 GPIOA0-3 (PWM0-3) GPIOA4 (PWM4, TA2, FAULT1) 1 GPIOA5 (PWM5, TA3, FAULT2) PWM or TMRA or GPIOA 1 GPIOA6 (FAULT0, TA0) 1 56F8033/56F802 1 1 GPIOB0 (SCLK0, SCL) SPI or I2C or PWM or TMRA or GPIOB 1 GPIOB1 (SS0, SDA) 1 GPIOB2 (MISO0, TA2, PSRC0) 1 GPIOB3 (MOSI0, TA3, PSRC1) 1 GPIOB4 (TA0, PSRC2, CLKO) SCI or PWM or I2C or TMRA or SPI or GPIOB 1 GPIOB5 (TA1, FAULT3, CL
2.2 56F8033/56F8023 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 26 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VSS 13 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.
56F8033/56F8023 Signal Pins Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOA1 28 (PWM1) Type Input/ Output State During Reset Input, internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM1 — This is one of the six PWM output pins. After reset, the default state is GPIOA1.
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOA5 20 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM5) Output PWM5 — This is one of the six PWM output pins.
56F8033/56F8023 Signal Pins Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOB0 21 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SCLK0) Input/ Output QSPI0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOB2 17 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO0) Input/ Output QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
56F8033/56F8023 Signal Pins Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOB4 19 Type Input/ Output (TA010) Input/ Output (PSRC2) Input (CLKO) Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TA0 — Timer A, Channel 0 PSRC2 — External PWM signal source input for the complementary PWM0/PWM1 pair.
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOB6 1 Type Input/ Output (RXD0) Input (SDA11) Input/ Output (CLKIN) Input State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Receive Data 0 — QSCI0 receive data input. Serial Data — This pin serves as the I2C serial data line.
56F8033/56F8023 Signal Pins Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. GPIOC1 11 (ANA1) Type Input/ Output State During Reset Input Analog Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA1 — Analog input to ADC A, Channel 1. After reset, the default state is GPIOC1.
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description Return to Table 2-2 TDI 30 (GPIOD0) Input Input, internal pull-up enabled Input/ Output Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin.
Overview Part 3 OCCS 3.1 Overview The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802X and 56F803X Peripheral Reference Manual. 3.
The 56F8000 family devices’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CTRL) Divide-by Register (OCCS_DIVBY) Status Register (OCCS_STAT) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802X and 56F803X Peripheral Reference Manual. 3.
Ceramic Resonator Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 KΩ Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg Ω CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz.
56F8033/56F8023 CLKMODE = 1 XTAL EXTAL External Clock GND or GPIO Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input.
Interrupt Vector Table Table 4-1 Chip Memory Configurations On-Chip Memory 56F8033 56F8023 Use Restrictions Program Flash (PFLASH) 32K x 16 16K x 16 or 64KB or 32KB Erase/Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4K x 16 or 8KB 2K x 16 or 4KB Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8033/56F8023’s reset and interrupt priority structure, including on-chip peripherals.
Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data, and Address Buffers Empty 20 - 23 Reserved GPIOD 24 0-2 P:$30 GPIOD GPIOC 25 0-2 P:$32 GPIOC GPIOB 26 0-2 P:$34 GPIOB GPIOA 27 0-2 P:$36 GPIOA QSPI0 28 0-2 P:$38 QSPI0 Receiver Full 29 0-2 P:$3A QSPI0 30 - 31 QSP
Program Map 4.3 Program Map The Program Memory map is shown inTable 4-3 and Table 4-4. Table 4-3 Program Memory Map1 at Reset for 56F8033 Begin/End Address Memory Allocation P: $1F FFFF P: $00 9000 RESERVED P: $00 8FFF P: $00 8000 On-Chip RAM2 8KB P: $00 7FFF P: $00 0000 Internal Program Flash 64KB Cop Reset Address = $00 0002 Boot Location = $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.
Table 4-5 Data Memory Map1 for 56F8033 (Continued) Begin/End Address Memory Allocation X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 8800 RESERVED X:$00 87FF X:$00 8000 RESERVED X:$00 7FFF X:$00 1000 RESERVED X:$00 0FFF X:$00 0000 On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1.
EOnCE Memory Map Program Data EOnCE Reserved Reserved RAM Peripherals Dual Port RAM Reserved Flash RAM Figure 4-1 Dual Port RAM for 56F8033 Program Data EOnCE Reserved Reserved RAM Peripherals Flash Dual Port RAM Reserved Reserved RAM Figure 4-2 Dual Port RAM for 56F8023 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-7 EOnCE Memory Map (Continued) Address X:$FF FFFC Register Acronym OCLSR Core Lock / Unlock Status Register X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 Register Name Reserved OCR Control Register X:$FF FF9F Instruction Step Counter X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9D OSR Status Register X:$FF FF9C OBASE Peripheral Base Address Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9A OTBPR Trace Buffer Pointer Register X:$FF FF99 Trace Buffer Regi
Peripheral Memory-Mapped Registers Table 4-8 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number Timer A TMRA X:$00 F000 4-9 ADC ADC X:$00 F080 4-10 PWM PWM X:$00 F0C0 4-11 ITCN ITCN X:$00 F0E0 4-12 SIM SIM X:$00 F100 4-13 COP COP X:$00 F120 4-14 CLK, PLL, OSC OCCS X:$00 F130 4-15 Power Supervisor PS X:$00 F140 4-16 GPIO Port A GPIOA X:$00 F150 4-17 GPIO Port B GPIOB X:$00 F160 4-18 GPIO Port C GPIOC X:$00 F170 4-19 GPI
Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym TMRA0_FILT Address Offset $B Register Description Input Filter Register Reserved TMRA0_ENBL $F Timer Channel Enable Register TMRA1_COMP1 $10 Compare Register 1 TMRA1_COMP2 $11 Compare Register 2 TMRA1_CAPT $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCTRL $17 Status and Control Re
Peripheral Memory-Mapped Registers Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA3_SCTRL $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_CSCTRL $3A Comparator Status and Control Register TMRA3_FILT $3B Input Filter Register Reserved Table 4-10 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register
Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_RSLT14 $1A Result Register 14 ADC_RSLT15 $1B Result Register 15 ADC_LOLIM0 $1C Low Limit Register 0 ADC_LOLIM1 $1D Low Limit Register 1 ADC_LOLIM2 $1E Low Limit Register 2 ADC_LOLIM3 $1F Low Limit Register 3 ADC_LOLIM4 $20 Low Limit Register 4 ADC_LOLIM5 $21 Low Limit Register 5 ADC_LOLIM6 $22 Low Limit Register 6 ADC_LOLIM7 $2
Peripheral Memory-Mapped Registers Table 4-11 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_OUT $3 Output Control Register PWM_CNTR $4 Counter Register PWM_CMOD $5 Counter Modulo Register PWM_VAL0 $6 Value Register 0 PWM_VAL1 $7 Value Register 1 PWM_VAL2 $8 Value Register 2 PWM_VAL3 $9 Value Register 3 PWM_VAL4 $A Value Register 4 PWM_VAL5 $B Value Register 5 PWM_DTIM0 $C Dead Time Regis
Table 4-12 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F0E0) Register Acronym Address Offset Register Description ITCN_FIM0 $8 Fast Interrupt Match 0 Register ITCN_FIVAL0 $9 Fast Interrupt Vector Address Low 0 Register ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register ITCN_FIM1 $B Fast Interrupt Match 1 Register ITCN_FIVAL1 $C Fast Interrupt Vector Address Low 1 Register ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register ITCN_IRQP0 $E IRQ
Peripheral Memory-Mapped Registers Table 4-13 SIM Registers Address Map (Continued) (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description Reserved SIM_GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB SIM_GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB Reserved SIM_ISS0 $18 Internal Source Select Register 0 for PWM SIM_ISS1 $19 Internal Source Select Register 1 for DACs SIM_ISS2 $1A Internal Source Select Register 2 for TMRA Reserved Table 4-14 Computer Oper
Table 4-17 GPIOA Registers Address Map (GPIOA_BASE = $00 F150) Register Acronym GPIOA_PUPEN Address Offset $0 Register Description Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register GPIOA_IASSRT $4 Interrupt Assert Register GPIOA_IEN $5 Interrupt Enable Register GPIOA_IEPOL $6 Interrupt Edge Polarity Register GPIOA_IPEND $7 Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register GP
Peripheral Memory-Mapped Registers Table 4-19 GPIOC Registers Address Map (GPIOC_BASE = $00 F170) Register Acronym Address Offset Register Description GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IEPOL $6 Interrupt Edge Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register GPIOC
Table 4-20 GPIOD Registers Address Map (GPIOD_BASE = $00 F180) Register Acronym Address Offset Register Description GPIOD_PUPEN $0 Pull-up Enable Register GPIOD_DATA $1 Data Register GPIOD_DDIR $2 Data Direction Register GPIOD_PEREN $3 Peripheral Enable Register GPIOD_IASSRT $4 Interrupt Assert Register GPIOD_IEN $5 Interrupt Enable Register GPIOD_IEPOL $6 Interrupt Edge Polarity Register GPIOD_IPEND $7 Interrupt Pending Register GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register
Peripheral Memory-Mapped Registers Table 4-23 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0) Register Acronym Address Offset Register Description DAC0_CTRL $0 Control Register DAC0_DATA $1 Data Register DAC0_STEP $2 Step Register DAC0_MINVAL $3 Minimum Value Register DAC0_MAXVAL $4 Maximum Value Register Table 4-24 Comparator A Registers Address Map (CMPA_BASE = $00 F1E0) Register Acronym Address Offset Register Description CMPA_CTRL $0 Control Register C
Table 4-27 Queued Serial Peripheral Interface 0 Registers Address Map (QSPI0_BASE = $00 F220) Register Acronym Address Offset Register Description QSPI0_SCTRL $0 Status and Control Register QSPI0_DSCTRL $1 Data Size and Control Register QSPI0_DRCV $2 Data Receive Register QSPI0_DXMIT $3 Data Transmit Register QSPI0_FIFO $4 FIFO Control Register QSPI0_DELAY $5 Delay Register Table 4-28 I2C Registers Address Map (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description
Peripheral Memory-Mapped Registers Table 4-28 I2C Registers Address Map (Continued) (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_ENBL $36 Enable Register I2C_STAT $38 Status Register I2C_TXFLR $3A Transmit FIFO Level Register I2C_RXFLR $3C Receive FIFO Level Register I2C_TXABRTSRC $40 Transmit Abort Status Register 56F8033/56F8023 Data Sheet, Rev.
Table 4-29 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FM_CLKDIV $0 Clock Divider Register FM_CNFG $1 Configuration Register $2 Reserved FM_SECHI $3 Security High Half Register FM_SECLO $4 Security Low Half Register $5 - $9 FM_PROT $10 $11 - $12 Reserved Protection Register Reserved FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 - $17 FM_DATA $18 $19 - $A FM_IFROPT_1 FM_TSTSIG Reserved Data Buffe
Functional Description For further information, see Table 4-2, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level.
Table 5-2 Interrupt Priority Encoding 5.3.3 IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority 11 Priority 2 or 3 Priority 3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2.
Block Diagram 5.4 Block Diagram any0 Priority Level INT1 Level 0 64 -> 6 Priority Encoder 2 -> 4 Decode 6 INT VAB CONTROL any3 Level 3 IACK SR[9:8] Priority Level INT64 IPIC 64 -> 6 Priority Encoder 6 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default.
system level and the address offset is defined at the module level. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F0E0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.5 IPR5 $5 Interrupt Priority Register 5 5.6.
Register Descriptions Add.
5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 Read 15 14 13 PLL IPL Write RESET 0 0 12 11 10 0 0 0 0 LVI IPL 0 0 9 8 RX_REG IPL 0 0 7 6 TX_REG IPL 0 0 5 4 TRBUF IPL 0 0 3 2 BKPT_U IPL 0 0 1 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.
Register Descriptions 5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.
5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read 15 14 GPIOD IPL Write RESET 0 0 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 FM_CBE IPL 0 0 3 2 FM_CC IPL 0 0 1 0 FM_ERR IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
Register Descriptions 5.6.2.5 FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0 This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
5.6.3.4 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6 This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for the GPIOA IRQ.
Register Descriptions 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14 This field is used to set the interrupt priority level for the I2C Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 Reserved—Bits 13–6 This bit field is reserved. Each bit must be set to 0. 5.6.4.
5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 TMRA_3 IPL Write RESET 0 0 13 12 TMRA_2 IPL 0 0 11 10 TMRA_1 IPL 0 0 9 8 TMRA_0 IPL 0 0 7 6 I2C_STAT IPL 0 0 5 4 I2C_TX IPL 0 0 3 2 I2C_RX IPL 0 0 1 0 I2C_GEN IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ.
Register Descriptions 5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
• 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 15 14 Read 0 0 0 0 Write RESET 13 12 PIT0 IPL 0 0 11 10 COMPB IPL 0 0 9 8 COMPA IPL 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR6) 5.6.6.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 5.6.6.
Register Descriptions 5.6.6.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 Read 0 0 0 0 0 0 0 0 Write RESET 11 10 PWM_F IPL 0 9 8 PWM_RL IPL 0 0 0 7 6 ADC_ZC IPL 0 0 5 4 ADCB_CC IPL 0 0 3 2 ADCA_CC IPL 0 0 1 0 0 0 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Reserved—Bits 15–12 This bit field is reserved. Each bit must be set to 0. 5.6.7.
5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
Register Descriptions 5.6.9 Fast Interrupt Match 0 Register (FIM0) Base + $8 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 2 1 0 0 0 FAST INTERRUPT 0 Write RESET 3 0 0 0 0 Figure 5-11 Fast Interrupt Match 0 Register (FIM0) 5.6.9.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 5.6.9.
5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.
Register Descriptions 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.
5.6.16.1 IRQ Pending (PENDING)—Bits 32–17 These register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
Register Descriptions 5.6.19.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core.
5.6.19.5 Reserved—Bits 4-2 This bit field is reserved. Each bit must be set to 1. 5.6.19.6 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 5.7 Resets 5.7.1 General Table 5-5 Reset Summary Reset Priority Core Reset 5.7.2 Source Characteristics RST Core reset from the SIM Description of Reset Operation 5.7.2.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM.
• Introduction SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module’s functions are discussed in more detail in the following sections. 6.
6.3 Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.3.
Register Descriptions Add.
Reserved 0 = Read as 0 = Read as 1 1 = Reserved Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 6.3.1.
Register Descriptions 6.3.2 SIM Reset Status Register (SIM_RSTAT) This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs.
6.3.2.7 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow.
Register Descriptions 6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption.
Base + $A 15 14 13 12 11 10 Read 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 9 8 PWM3 PWM2 0 0 7 6 PWM1 PWM0 0 0 5 4 3 CLK DIS 1 2 1 0 0 0 CLKOSEL 0 0 0 Figure 6-8 CLKO Select Register (SIM_CLKOUT) 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.2 • • 0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock 6.3.7.
Register Descriptions peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it. Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured.
Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register is set to 1. Base + $C Read 15 14 13 12 CMPB CMPA DAC1 DAC0 0 0 0 0 11 10 0 9 8 7 0 0 0 ADC 6 5 4 0 I2C 3 2 0 QSCI0 1 0 0 QSPI0 PWM Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0) 6.3.9.
Register Descriptions 6.3.9.9 Reserved—Bit 5 This bit field is reserved. It must be set to 0. 6.3.9.10 • • QSCI 0 Clock Enable (QSCI0)—Bit 4 0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled) 1 = The clock is enabled to the QSCI0 module 6.3.9.11 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.9.
6.3.10.4 • • 0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled) 1 = The clock is enabled to the Timer A3 module 6.3.10.5 • • Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1 0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled) 1 = The clock is enabled to the Timer A1 module 6.3.10.
Register Descriptions 6.3.11.2 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.3 • • Digital-to-Analog Converter 0 Clock Stop Disable (DAC1_SD)—Bit 13 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2 Each bit controls clocks to the indicated peripheral. • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.13 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.11.
Register Descriptions • 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.6 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.
Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ISAL[23:22] Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.13.1 Reserved—Bits 15—2 This bit field is reserved. Each bit must be set to 0. 6.3.13.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. 6.3.
Register Descriptions Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 PCEP Write RESET 2 0 0 GIPSP 0 0 0 Figure 6-17 Protection Register (SIM_PROT) 6.3.15.1 Reserved—Bits 15–4 This bit field is reserved. Each bit must be set to 0. 6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2 These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
GPIOA6_PEREN Register SIM_GPSA0 Register PWM FAULT0 GPIOA6 0 GPIOA6 pin 0 1 1 Timer A0 Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one of these I/O must be configured to control that peripheral function.
Register Descriptions 6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10 This field selects the alternate function for GPIOA5. • • • • 00 = PWM5 - PWM5 (default) 01 = FAULT2 - PWM FAULT2 Input 10 = TA3 - Timer A3 11 = Reserved 6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8 This field selects the alternate function for GPIOA4. • • • • 00 = PWM4 - PWM4 (default) 01 = FAULT1 - PWM FAULT1 Input 10 = TA2 - Timer A2 11 = Reserved 6.3.16.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0.
6.3.17.3 Configure GPIOB5 (GPS_B5)—Bits 12–11 This field selects the alternate function for GPIOB5. • • • • 00 = TA1 - Timer A1 (default) 01 = FAULT3 - PWM FAULT3 Input 10 = CLKIN - External Clock Input 11 = Reserved 6.3.17.4 Configure GPIOB4 (GPS_B4)—Bits 10–8 This field selects the alternate function for GPIOB4. • • • • • • • 000 = TA0 - Timer A0 (default) 001 = CLKO - Clock Output 010 = Reserved 011 = TB0 - Timer B0 100 = PSRC2 - PWM4 / PWM5 Pair External Source 11x = Reserved 1x1 = Reserved 6.3.
Register Descriptions 6.3.17.9 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.17.10 Configure GPIOB0 (GPS_B0)—Bits 0 This field selects the alternate function for GPIOB0. • 0 = SCLK0 - QSPI0 Serial Clock (default) • 1 = SCL - I2C Serial Clock 6.3.18 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
GPIOA5_PEREN Register SIM_GPSA0 Register GPIOA5 SIM_IPS0 Register 0 PWM5 GPIOA5 pin 00 0 1 01 PWM FAULT2 Timer A3 10 1 Comparator A Output (Internal) Figure 6-22 Overall Control of Signal Source using SIM_IPSn Control IPSn settings should not be altered while an affected peripheral is in an enabled (operational) configuration. See the 56F802X and 56F803X Peripheral Reference Manual for details.
Register Descriptions 6.3.19.5 Reserved—Bits 10–9 This bit field is reserved. Each bit must be set to 0. 6.3.19.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)—Bits 8–6 This field selects the alternate input source signal to feed PWM input PSRC2 as the PWM4/PWM5 pair source.
6.3.19.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)—Bits 2–0 This field selects the alternate input source signal to feed PWM input PSRC0 as the PWM0/PWM1 pair source.
Register Descriptions • 11x = Reserved 6.3.20.3 Select Peripheral Input Source for SYNC Input to DAC 0 (ISS1_DSYNC0)—Bits 2–0 This field selects the alternate input source signal to feed DAC0 SYNC input.
6.3.21.5 Reserved—Bits 7–5 This bit field is reserved. Each bit must be set to 0. 6.3.21.6 Select Peripheral Input Source for TA1 (IPS2_TA1)—Bit 4 This field selects the alternate input source signal to feed Quad Timer A, input 1. • • 0 = I/O pin (External) - Use Timer A1 input/output pin 1 = CMPAO (Internal) - Use Comparator A output 6.3.21.7 Reserved—Bits 3–0 This bit field is reserved. Each bit must be set to 0.
Power-Saving Modes 6.5 Power-Saving Modes The 56F8033/56F8023 operates in one of five Power-Saving modes, as shown in Table 6-2. Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications.
default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
Clocks EXTENDED_POR JTAG POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock Memory Subsystem CLKGEN_RST OCCS COMBINED_RST External RESET IN (active low) PERIP_RST Delay 32 OSC_CLK Clock RESET Peripherals pulse shaper Delay 32 sys clocks COP_TOR (active low) SW Reset pulse shaper COP_LOR (active low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles.
The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset.
Interrupts Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-27 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts.
security mode is enabled, the 56F8023 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU.
Product Analysis in order to return to normal unsecured operation. Power-on reset will also reset both. The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.
Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 29 Defaults to A0 GPIOA1 PWM1 28 Defaults to A1 GPIOA2 PWM2 23 Defaults to A2 GPIOA3 PWM3 24 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 22 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 20 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2.
Reset Values Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB6 RXD0 / SDA / CLKIN 1 SIM register SIM_GPS is used to select between RXD0, SDA, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B6 GPIOB7 TXD0 / SCL 3 SIM register SIM_GPS is used to select between TXD0 and SCL.
Add.
Reset Values Add.
Add.
Reset Values Add.
Part 9 Joint Test Action Group (JTAG) 9.1 56F8033/56F8023 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802X and 56F803X Peripheral Reference Manual. Part 10 Specifications 10.
General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.
Table 10-2 56F8033/56F8023 ESD Protection Characteristic Min Typ Max Unit ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 750 — — V Table 10-3 LQFP Package Thermal Characteristics6 Characteristic Comments Symbol Value (LQFP) Unit Notes RθJA 41 °C/W 2 Junction to ambient Natural convection Single layer board (1s) Junction to ambient Natural convection Four layer board (2s2p) RθJMA 34 °C/W 1, 2 Junction to ambient (@200 ft/min) Single layer board (1s)
General Characteristics Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Symbol Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V VREFHx 3.0 VDDA V Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 0 0.
10.2 DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4V to 5.
DC Electrical Characteristics 2.0 0.0 µA - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Volt Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled) Table 10-6 Current Consumption per Power Supply Pin Typical @ 3.3V, 25°C Mode Maximum@ 3.6V, 25°C Conditions IDD1 IDDA IDD1 IDDA RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled.
Table 10-6 Current Consumption per Power Supply Pin (Continued) Typical @ 3.3V, 25°C Mode Maximum@ 3.
AC Electrical Characteristics measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8. Table 10-8. Regulator Parameters Characteristic Short Circuit Current Short Circuit Tolerance (VCAP shorted to ground) Symbol Min Typical Max Unit ISS — 450 650 mA TRSC — — 30 minutes 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5.
10.4 Flash Memory Characteristics Table 10-9 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — 40 μs Erase time 2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F802X and 56F803X Peripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory. 10.
Phase Locked Loop Timing 10.6 Phase Locked Loop Timing Table 10-11 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 — MHz Internal reference relaxation oscillator frequency for the PLL frosc — 8 — MHz PLL output frequency2 (24 x reference frequency) fop 96 192 — MHz PLL lock time3 tplls — 40 100 µs Accumulated jitter using an 8MHz external crystal as the PLL source4 JA — — 0.
4. See Figure 10-5 8.16 8.08 MHz 8 7.92 7.84 -50 -25 0 25 50 75 100 125 150 175 Degrees C (Junction) Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim 56F8033/56F8023 Data Sheet, Rev.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All address and data buses described here are internal.
10.9 Serial Peripheral Interface (SPI) Timing Table 10-14 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 125 62.5 — — ns ns — 31 — — ns ns — 125 — — ns ns 50 31 — — ns ns 50 31 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing 1. Parameters listed are guaranteed by design. SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in tDI MOSI (Output) Master MSB out Bits 14–1 tDV Bits 14–1 tF LSB in tDI(ref) Master LSB out tR Figure 10-7 SPI Master Timing (CPHA = 0) 56F8033/56F8023 Data Sheet, Rev.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Master MSB out tDH Bits 14–1 tDV Bits 14– 1 tF LSB in tDI(ref) Master LSB out tR Figure 10-8 SPI Master Timing (CPHA = 1) 56F8033/56F8023 Data Sheet, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-9 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input) t
10.10 Quad Timer Timing Table 10-15 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-11 Timer input high / low period PINHL 1T + 3 — ns 10-11 Timer output period POUT 125 — ns 10-11 POUTHL 50 — ns 10-11 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing 10.11 Serial Communication Interface (SCI) Timing Table 10-16 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width TXDPW 0.965/BR 1.
10.12 Inter-Integrated Circuit Interface (I2C) Timing Table 10-17 I2C Timing Standard Mode Characteristic Fast Mode Symbol Unit Minimum Maximum Minimum Maximum fSCL 0 100 0 400 kHz tHD; STA 4.0 — 0.6 — μs LOW period of the SCL clock tLOW 4.7 — 1.3 — μs HIGH period of the SCL clock tHIGH 4.0 — 0.6 — μs Set-up time for a repeated START condition tSU; STA 4.7 — 0.6 — μs Data hold time for I2C bus devices tHD; DAT 01 3.452 01 0.
JTAG Timing SDA tf tLOW tf tSU; DAT tr tHD; STA tSP tr tBUF SCL S tSU; STA tHD; STA tHD; DAT tHIGH tSU; STO SR P S Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus 10.
TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 10-16 Test Access Port Timing Diagram 56F8033/56F8023 Data Sheet, Rev.
Analog-to-Digital Converter (ADC) Parameters 10.14 Analog-to-Digital Converter (ADC) Parameters Table 10-19 ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC. 10.15 Equivalent Circuit for ADC Inputs Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFHx- VREFLx) / 2, while the other charges to the analog input voltage.
Digital-to-Analog Converter (DAC) Parameters Table 10-20 CMP Parameters Characteristic Conditions/Comments Symbol Min Typ Max Unit Input Propagation Delay tPD — 35 45 ns Power-up time tCPU — TBD TBD 1. No guaranteed specification within 0.1V of VDDA or VSSA 10.
2. LSB = 0.806mV 56F8033/56F8023 Data Sheet, Rev.
Power Consumption 10.18 Power Consumption See Section 10.1 for a list of IDD requirements for the 56F8033/56F8023. This section provides additional detail which can be used to optimize power consumption for a given application.
• Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations.
56F8033/56F8023 Package and Pin-Out Information Part 11 Packaging 11.1 56F8033/56F8023 Package and Pin-Out Information VCAP VDD ORIENTATION MARK GPIOB6 / RXD0 / SDA / CLKIN GPIOA3 / PWM3 PIN 25 GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL VSS GPIOA1 / PWM1 GPIOA0 / PWM0 TDI / GPIOD0 TMS / GPIOD3 TDO / GPIOD1 This section contains package and pin-out information for the 56F8033/56F8023. This device comes in a 32-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8033/56F8023 32-Pin LQFP Package Identification by Pin Number1 Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 GPIOB6 RXD0 / SDA / CLKIN 9 VSSA 17 GPIOB2 MISO0 / TA2 / PSRC0 25 VCAP 2 GPIOB1 SS0 / SDA 10 GPIOC2 ANA2 / VREFHA 18 GPIOA6 FAULT0 / TA0 26 VDD 3 GPIOB7 TXD0 / SCL 11 GPIOC1 ANA1 19 GPIOB4 TA0 / CLKO / PSRC2 27 VSS 4 GPIOB5 TA1 / FAULT3 / CLKIN 12 GPIOC0 ANA0 & CMPAI3 20 GPIOA5 PWM5 / TA3 / FAULT2 28 GPIOA1 PWM1 5 GPIO
A –T–, –U–, –Z– 56F8033/56F8023 Package and Pin-Out Information 4X A1 0.20 (0.008) AB T–U Z 32 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD Q_ GAUGE PLANE H 0.250 (0.010) C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3.
Please see www.freescale.com for the most current case outline. 56F8033/56F8023 Data Sheet, Rev.
Thermal Design Considerations Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Electrical Design Considerations • Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs.
Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table. Note: This table comprises all peripherals used in the 56F803x and 56F802x family; some of the peripherals described here may not be present on this device.
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Timeout Register TOUT COPTO COP_TOUT COPTO COPTO 0XF121 Counter Register CNTR COPCTR COP_CNTR COPCTR COPCTR 0XF122 56F8033/56F8023 Data Sheet, Rev.
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Inter-Integrated Circuit Interface (I2C) Module Control Register CTRL I2C_CTRL I2C_IBCR I2C_IBCR 0xF280 Target Address Register TAR IBCR I2C_TAR I2CTAR I2C_TAR 0xF282 Slave Address Register SAR I2C_SAR I2CSAR I2C_SAR 0xF242 Data Buffer & Command Register DATA I2C_DATA I2C_
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Clear Receive Done Interrupt Register Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End CLRRXDONE I2C_CLR_RXDONE I2C_CLR_RXDONE 0xF2AC CLRACT I2C_CLRACTIVITY I2C_CLRACTIVITY 0xF2AE Clear Stop Detect Interrupt Register CLRSTPDET I2C_CLR_STOPDET I2C_CLR_STOPDET 0xF2B0 Clear Start Detect Interrupt Re
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name Security Low Half Register New Acronym Legacy Acronym New Acronym Legacy Acronym SECLO FMSECL FM_SECLO FMSECL Processor Expert Acronym Memory Address Start End FMSECL 0xF404 Protection Register PROT FMPROT FM_PROT FMPROT FMPROT 0xF410 User Status Register USTAT FMUSTAT FM_USTAT FMUSTAT FMUSTAT 0xF413 Command Register CMD FMCMD FM_CMD FMCMD FMCMD 0xF414 Data Buffer Reg
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Pulse Width Modulator (PWM) Module Control Register CTRL PMCTL Fault Control Register FCTRL Fault Status/Acknowledge Regis.
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Transmitter Message Abort Acknowledge Register TAAK CAN_TAAK CANTAAK 0XF809 Transmitter FIFO Selection Register TBSEL CAN_TBSEL CANTBSEL 0XF80A Identifier Acceptance Control Register IDAC CAN_IDAC CANIDAC 0XF80B Miscellaneous Register MISC CAN_MISC CANMISC 0XF80D Receive Err
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