Datasheet

Functional Description
MC13783 Technical Data, Rev. 3.5
Freescale Semiconductor 29
4.3.3.2 Clock Modes
The stereo DAC incorporates a PLL to generate the proper clocks in master and in slave modes. The PLL
requires an external C//RC loop filter.
In Master Mode, the PLL of the Stereo DAC generates FS and BCL signal based on the reference
frequency applied through one of the CLI inputs. The CLI frequencies supported are 3.6864 MHz, 12
MHz, 13 MHz, 15.36 MHz, 16.8 MHz, 26 MHz and 33.6 MHz. The PLL will also generate its own master
clock MCL used by the stereo DAC itself.
In Slave Mode, FS and BCL are applied to the MC13783 and the MCL is internally generated by the PLL
based on either FS or BCL.
A special mode is foreseen where the PLL is bypassed and CLI can be used as the MCL signal. In this
mode, MCLK must be provided with the exact ratio to FS, depending on the sample rate selected.
In the network mode, it’s possible to select up to 8 time slots (4 time slot pairs).
Figure 7. Stereo DAC PLL Block Diagram
Table 15. Stereo DAC Sample Rate Selection SPI Bits
SR3 SR2 SR1 SR0 FS N
FS
MCL N
B
BCL
000080005124096k 16 256k
0001110255125644.8k16352.8k
0010120005126144k 16 384k
0011160002564096k 8 512k
0100220502565644.8k 8 705.6k
0101240002566144k 8 768k
0110320001284096k 4 1024k
0111441001285644.8k 41411.2k
CLIB
CLI
A
FS1
BCL2
BCL1
FS2
STDCSSISEL
STDCCLKSEL
1
NR
1
NF
1
NO
NS
NB
1
NFS
VCO
LPF
∅
internal master clock MCLint
STDCSM=1 &
STDCCLK=101
STDCSM=0
STDCCLK[3:0]
STDCSM=0
MCL
STDCSM=1 &
STDCCLK=101