Datasheet

Functional Description
MC13783 Technical Data, Rev. 3.5
28 Freescale Semiconductor
4.3.2.3 Clock Modes
In master mode the CLI is divided internally to generate the BCL and FS signals. In slave mode these
clocks have to be supplied and in that case there is no imposed relationship between BCL and the other
clocks as long as it is high enough to support the number of time slots requested. The supported clock rates
are 13.0 MHz, 15.36 MHz, 16.8 MHz, 26.0 MHz and 33.6 MHz.
4.3.3 Stereo DAC
4.3.3.1 D/A Converter
The stereo DAC is based on a 16-bit linear left and right channel D/A converter with integrated filtering.
Table 13. Telephone CODEC D/A Performance Specifications
Parameter Condition Min Typ Max Units
Peak Output (+3 dBm0) single ended output REFC - 1 REFC + 1 V
CODEC PSRR with respect to B+,
20 Hz to 20 kHz,
80 90 — dB
Total Distortion
(noise and harmonic)
at 1.02 kHz, 0 dBm0,
20 kHz measurement BW out
65 75 — dB
Idle Channel Noise at CODEC output,
BW out = 20 kHz A weighted
—-78-74dBm0
Inband Spurious 0 dBm0 at 1.02 kHz to 3.4 kHz input.
300 Hz to 20.0 kHz
——-50dB
Table 14. Stereo DAC Main Performance Specifications
Parameter Condition Min Typ Max Units
Absolute Gain Input at 0 dBFS,
from 20 Hz to 20 kHz
-0.5 — +0.5 dB
L/R Gain
Mismatch
Input at -3 dBFS, 1.02 kHz — 0.2 0.3 dB
Dynamic Range (SNDR at -60 dBFS and 1.02 kHz) + 60 dB,
20 kHz BW out,
A weighted
92 96 — dB
Output PSRR with respect to battery,
input at 0 dBFS,
from 20 Hz to 20 kHz
A weighted
90——dB
Spurious input at -3 dBFS,
from 20 Hz to 20 kHz,
20 kHz BW out
Includes idle tones
——-75dB