Datasheet

Functional Description
MC13783 Technical Data, Rev. 3.5
20 Freescale Semiconductor
Figure 4. SPI Interface Timing Diagram
Table 6. SPI Interface Timing Specifications
Parameter Description T min (ns)
T
selsu
Time CS has to be high before the first rising edge of CLK 20
T
selhld
Time CS has to remain high after the last falling edge of CLK 20
T
sellow
Time CS has to remain low between two transfers 20
T
clkper
Clock period of CLK
1
1
Equivalent to a maximum clock frequency of 20 MHz.
50
T
clkhigh
Part of the clock period where CLK has to remain high 20
T
clklow
Part of the clock period where CLK has to remain low 20
T
wrtsu
Time MOSI has to be stable before the next rising edge of CLK 5
T
wrthld
Time MOSI has to remain stable after the rising edge of CLK 5
T
rdsu
Time MISO will be stable before the next rising edge of CLK 5
T
rdhld
Time MISO will remain stable after the falling edge of CLK 5
T
rden
Time MISO needs to become active after the rising edge of CS 5
T
rddis
Time MISO needs to become inactive after the falling edge of CS 5
Table 7. SPI Interface Logic IO Specifications
Parameter Condition Min Max Units
Input High CS, MOSI, CLK — 0.7*VCC VCC+0.5 V
Input Low CS, MOSI, CLK — 0 0.3*VCC V
Output Low MISO, INT Output sink 100 μA00.2V
Output High MISO, INT Output source 100 μA VCC-0.2 VCC V
Note: VCC refers to PRIVCC and SECVCC respectively.
CS
CLK
T
selsu
T
selhld
T
clkper
T
clkhigh
T
clklow
MOSI
MISO
T
wrtsu
T
wrthld
T
rdsu
T
rddis
T
rden
T
rdhld
T
sellow