Datasheet

Functional Description
MC13783 Technical Data, Rev. 3.5
Freescale Semiconductor 19
The default CS polarity is active high. The CS line must remain active during the entire SPI transfer. In
case the CS line goes inactive during a SPI transfer all data is ignored. To start a new SPI transfer, the CS
line must go inactive and then go active again. The MISO line will be tri-stated while CS is low.
Note that not all bits are truly writable. Refer to the individual subcircuit descriptions to determine the
read/write capability of each bit. All unused SPI bits in each register must be written to a zero. SPI
readbacks of the address field and unused bits are returned as zero. To read a field of data, the MISO pin
will output the data field pointed to by the 6 address bits loaded at the beginning of the SPI sequence.
Figure 2. SPI Transfer Protocol Single Read/Write Access
Figure 3. SPI Transfer Protocol Multiple Read/Write Access
4.1.1.3.2 SPI Requirements
The requirements for both SPI interfaces are equivalent. Therefore, all SPI bus names without prefix PRI
or SEC correspond to both SPI interfaces. The below diagram and table summarize the SPI electrical and
timing requirements. The SPI input and output levels are set independently via the PRIVCC and SECVCC
pins by connecting those to the proper supply.
CS
CLK
MOSI
MISO
Write_En Addr ess5 Address4 Address3 Address2 Address 1 Address 0 Data 23 Data 1 Data 0
Data 23 Data 1 Data 0
Data 22
Data 22
“Dead Bit”
24 Bits Data
24 Bits Data
24 Bits Data
24 Bits Data
Preamble
First Address
Preamble
A
nother Address
MOSI
MISO
CS