Datasheet
LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 9 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 14.5 “
Pin states in
different power modes”. For termination on unused pins, see Section 14.4 “Termination of unused pins”.
[2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
PIO0_14/
ACMP_I3/ADC_2
20 25
[2]
I; PU IO PIO0_14 — General-purpose port 0 input/output 14.
A ACMP_I3 — Analog comparator common input 3.
A ADC_2 — ADC input 2.
PIO0_15 11 15
[5]
I; PU IO PIO0_15 — General-purpose port 0 input/output 15.
PIO0_16 - 10
[4]
I; PU IO PIO0_16 — General-purpose port 0 input/output 16.
PIO0_17/ADC_9 2 32
[2]
I; PU IO PIO0_17 — General-purpose port 0 input/output 17.
A ADC_9 — ADC input 9.
PIO0_18/ADC_8 - 31
[2]
I; PU IO PIO0_18 — General-purpose port 0 input/output 18.
A ADC_8 — ADC input 8.
PIO0_19/ADC_7 - 30
[2]
I; PU IO PIO0_19 — General-purpose port 0 input/output 19.
A ADC_7 — ADC input 7.
PIO0_20/ADC_6 - 29
[2]
I; PU IO PIO0_20 — General-purpose port 0 input/output 20.
A ADC_6 — ADC input 6.
PIO0_21/ADC_5 - 28
[2]
I; PU IO PIO0_21 — General-purpose port 0 input/output 21.
A ADC_5 — ADC input 5.
PIO0_22/ADC_4 - 27
[2]
I; PU IO PIO0_22 — General-purpose port 0 input/output 22.
A ADC_4 — ADC input 4.
PIO0_23/ADC_3/
ACMP_I4
126
[2]
I; PU IO PIO0_23 — General-purpose port 0 input/output 23.
A ADC_3 — ADC input 3.
A ACMP_I4 — Analog comparator common input 4.
PIO0_24 - 14
[5]
I; PU IO PIO0_24 — General-purpose port 0 input/output 24.
PIO0_25 - 13
[5]
I; PU IO PIO0_25 — General-purpose port 0 input/output 25.
PIO0_26 - 12
[5]
I; PU IO PIO0_26 — General-purpose port 0 input/output 26.
PIO0_27 - 11
[5]
I; PU IO PIO0_27 — General-purpose port 0 input/output 27.
PIO0_28/
WKTCLKIN
-5
[3]
I; PU IO PIO0_28 — General-purpose port 0 input/output 28. This pin can
host an external clock for the self-wake-up timer. To use the pin as
a self-wake-up timer clock input, select the external clock in the
wake-up timer CTRL register. The external clock input is active in
all power modes, including deep power-down.
V
DD
15 19 - - Supply voltage for the I/O pad ring, the core voltage regulator, and
the analog peripherals.
VSS 16 33 - - Ground.
VREFN 17 20 - - ADC negative reference voltage.
VREFP 18 21 - - ADC positive reference voltage. Must be equal or lower than V
DD
.
Table 3. Pin description
Symbol
TSSOP20
HVQFN33
Reset
state
[1]
Type Description